DS2155GB/T&R Maxim Integrated, DS2155GB/T&R Datasheet - Page 24

• Manufacturer Part Number: DS2155GB/T&R
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2155GB/T&R

• Part # Aliases: 90-2155G-BTR

Signal Name:
Signal Description:
Signal Type:
Clock used to clock data through the receive-side framer. This pin is normally connected to RCLKO. Can be
internally connected to RCLKO by connecting the LIUC pin high.
4.3 Parallel Control Port Pins
Signal Name:
Signal Description:
Signal Type:
Flags host controller during conditions and events defined in the status registers. Active-low, open-drain output.
Signal Name:
Signal Description:
Signal Type:
A dual function pin. A 0-to-1 transition issues a hardware reset to the DS2155 register set. A reset clears all
configuration registers. Configuration register contents are set to 0. Leaving TSTRST high tri-states all output and
I/O pins (including the parallel control port). Set low for normal operation. Useful in board-level testing.
Signal Name:
Signal Description:
Signal Type:
Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
Signal Description:
Signal Type:
In nonmultiplexed bus operation (MUX = 0), these serve as the data bus. In multiplexed bus operation (MUX = 1),
these pins serve as an 8-bit multiplexed address/data bus.
Signal Name:
Signal Description:
Signal Type:
In nonmultiplexed bus operation (MUX = 0), these serve as the address bus. In multiplexed bus operation
(MUX = 1), these pins are not used and should be connected low.
Signal Name:
Signal Description:
Signal Type:
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the
RD (DS), ALE (AS), and WR (R/W) pins.
If BTS = 1, then these pins assume the function listed in parentheses ().
Signal Name:
Signal Description:
Signal Type:
In Intel mode, RD determines when data is read from the device. In Motorola mode, DS is used to write to the
device. See Bus Timing Diagrams.
RCLKI
Receive Clock Input
Input
INT
Interrupt
Output
TSTRST
Tri-State Control and Device Reset
Input
MUX
Bus Operation
Input
AD0 to AD7
Data Bus [D0 to D7] or Address/Data Bus
Input/Output
A0 to A6
Address Bus
Input
BTS
Bus Type Select
Input
RD (DS)
Read Input, Data Strobe
Input
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