DS32508-W Maxim Integrated, DS32508-W Datasheet
DS32508-W
Specifications of DS32508-W
Related parts for DS32508-W
DS32508-W Summary of contents
Page 1
... GENERAL DESCRIPTION The DS32506 (6 port), DS32508 (8 port), and DS32512 (12 port) line interface units (LIUs) are highly integrated, low-power, feature-rich LIUs for DS3, E3, and STS-1 applications. Each LIU port in these devices has independent receive and transmit paths, a jitter attenuator, full-featured ...
Page 2
... Loss-of-Signal (LOS) Detector............................................................................................................ 31 8.3.6 Framer Interface Format and the B3ZS/HDB3 Decoder .................................................................... 32 8.3.7 Power-Down........................................................................................................................................ 33 8.3.8 Input Failure Detection........................................................................................................................ 33 8.3.9 Jitter and Wander Tolerance............................................................................................................... 34 8.3.10 Jitter Transfer ...................................................................................................................................... 35 8 .....................................................................................................................35 ITTER TTENUATOR 8.5 BERT...........................................................................................................................................36 TABLE OF CONTENTS (BERT) F ...............................................................................12 EATURES I F .....................................................................12 NTERFACE EATURES I F ..................................................................12 NTERFACE EATURES ..........................................................................................................12 ............................................................................................................14 ........................................................................................................ 130 DS32506/DS32508/DS32512 ...
Page 3
... ELECTRICAL CHARACTERISTICS .............................................................................92 12. PIN ASSIGNMENTS....................................................................................................106 13. PACKAGE INFORMATION.........................................................................................127 13.1 484-L BGA (23 EAD MM X 14. THERMAL INFORMATION .........................................................................................128 15. ACRONYMS AND ABBREVIATIONS.........................................................................129 16. TRADEMARK ACKNOWLEDGEMENTS....................................................................129 17. DATA SHEET REVISION HISTORY ...........................................................................130 I ......................................................................43 NTERFACE I ...................................................................................44 NTERFACE ................................................................................................................46 ............................................................................................................47 ..............................................................................................................50 ..........................................................................................................62 R ..............................................................................................79 EGISTERS R ..............................................................................................80 EGISTERS 23 ) (56-G60038-001) .....................................................................127 130 DS32506/DS32508/DS32512 ...
Page 4
... Figure 12-4. DS32508 Pin Assignment, Hardware and Microprocessor Interfaces................................................ 115 Figure 12-5. DS32508 Pin Assignment, Hardware Interface Only .......................................................................... 117 Figure 12-6. DS32508 Pin Assignment, Microprocessor Interface Only ................................................................. 119 Figure 12-7. DS32506 Pin Assignment, Hardware and Microprocessor Interfaces................................................ 121 Figure 12-8. DS32506 Pin Assignment, Hardware Interface Only .......................................................................... 123 Figure 12-9 ...
Page 5
... Table 11-7. Transmitter Output Characteristics—E3 Mode....................................................................................... 97 Table 11-8. Parallel CPU Interface Timing ................................................................................................................ 98 Table 11-9. SPI Interface Timing ............................................................................................................................. 103 Table 11-10. JTAG Interface Timing........................................................................................................................ 105 Table 12-1. Pin Assignments Sorted by Signal Name for DS32506/DS32508/DS32512 ....................................... 106 Table 14-1. Thermal Properties, Natural Convection .............................................................................................. 128 Table 14-2. Theta-JA (θ ) vs. Airflow...................................................................................................................... 128 ...
Page 6
... Signals, October 1992 GR-253-CORE SONET Transport Systems: Common Generic Criteria, Issue 3, September 2000 Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 2, GR-499-CORE December 1998 GR-820-CORE Generic Digital Transmission Surveillance, Issue 2, December 1997 SPECIFICATION TITLE ANSI AT&T ETSI ITU-T TELCORDIA 6 of 130 DS32506/DS32508/DS32512 ...
Page 7
... Driver shaping CLAD AGC, B3ZS/ HDB3 Decoder ALB JA LLB B3ZS/ Wave- HDB3 Encoder Parallel and SPI Bus Interfaces 7 of 130 DS32506/DS32508/DS32512 JTAG Port 12) RCLKn RPOSn / RDATn Pattern RNEGn / RLCVn Detector DLB RCLKI Pattern TCLKI Generator TCC TCLKn TPOSn / TDATn ...
Page 8
... APPLICATION EXAMPLE Figure 3-1. 12-Port Unchannelized DS3/E3 Card DS3/E3/STS-1 DS32512 DS31912 77.76MHz TELECOM BUS 12-PORT 12-PORT DS3/E3/STS-1 LIU MAPPER 8 of 130 DS32506/DS32508/DS32512 ...
Page 9
... DETAILED DESCRIPTION The DS32506 (6 port), DS32508 (8 port), and DS32512 (12 port) LIUs perform the functions necessary for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit paths and a built-in jitter attenuator. The receiver performs clock and data recovery from a B3ZS- or HDB3-coded alternate mark inversion (AMI) signal and monitors for loss of the incoming signal ...
Page 10
... Shorthand Notations. The notation “DS325xx” throughout this data sheet refers to either the DS32506, DS32508, or DS32512. This data sheet is the specification for all three devices. The LIUs on the DS325xx devices are identical. For brevity, this document uses the pin name and register name shorthand “NAMEn,” where “n” stands in place of the LIU port number ...
Page 11
... Fully integrated, requires no external components Meets all applicable ANSI, ITU, ETSI, and Telcordia jitter transfer and output jitter requirements Can be placed in the transmit path, receive path or disabled Programmable FIFO depth: 16, 32, 64, or 128 bits Overflow and underflow status indications DS32506/DS32508/DS32512 11 of 130 ...
Page 12
... Analog local loopback—ALB (transmit line output to receive line input) Diagnostic local loopback—DLB (transmit framer interface to receive framer interface) Line loopback—LLB (receive clock and data recover to transmit waveshaping) Optional AIS generation on the line side of the loopback during diagnostic loopback DS32506/DS32508/DS32512 32) and repetitive patterns from ...
Page 13
... LMn[1:0], JAS[1:0], JAD[1:0], LBn[1:0], and LBS. (HW = 1), device configuration can be controlled by input pins, while WR control signals) while IFSEL[ specifies a Motorola 130 DS32506/DS32508/DS32512 (HW = 0), all the pins in IFSEL ...
Page 14
... Short Pin Descriptions n = port number ( for DS32512 for DS32508 for DS32506 input, Ipu = input with internal pullup resistor, Ipd = input with internal pulldown resistor analog input, I/O = bidirectional in/out, I/Opd = bidirectional in/out with internal pulldown resistor output high-impedance output (needs an external pullup or pulldown resistor to keep the node from floating analog output (high impedance power supply or ground. All unused input pins without pullup should be tied low. Note: All internal pullup resistors are 50k Ω ...
Page 15
... POWER SUPPLY AND GROUND PINS Digital Core 1.8V Power, 1.8V ±5% VDD18 P I/O 3.3V Power, 3.3V ±5% VDD33 P VSS P Ground for VDD18 and VDD33 Jitter Attenuator 1.8V Power, 1.8V ±5% (Port n) JVDDn P JVSSn P Jitter Attenuator Ground (Port n) Receive 1.8V Power, 1.8V ±5% (Port n) RVDDn P FUNCTION SPI SERIAL INTERFACE CLAD JTAG 15 of 130 DS32506/DS32508/DS32512 ...
Page 16
... NAME TYPE RVSSn P Receive Ground (Port n) Transmit 1.8V Power, 1.8V ±5% (Port n) TVDDn P TVSSn P Transmit Ground (Port n) CLAD 1.8V ±5% CVDD P CVSS P CLAD Ground MANUFACTURING TEST MT[10:0] Test Manufacturing Test Pins DS32506/DS32508/DS32512 FUNCTION 16 of 130 ...
Page 17
... Detailed Pin Descriptions n = port number ( for DS32512 for DS32508 for DS32506 input, Ipu = input with internal pullup resistor, Ipd = input with internal pulldown resistor analog input, I/O = bidirectional in/out, I/Opd = bidirectional in/out with internal pulldown resistor output high-impedance output (needs an external pullup or pulldown resistor to keep the node from floating analog output (high impedance), P= power supply or ground. All unused input pins without pullup should be tied low. Note: All internal pullup resistors are 50k Ω ...
Page 18
... WR control signals) R control signals) R/W 6 for details. JTRST is low, all the digital output and bidirectional pins are placed in the RST RST is low. should be held low for at least two reference clock 18 of 130 DS32506/DS32508/DS32512 6 for details. DS control signals control signals) ...
Page 19
... TCLK. TDAT and TNEG are sampled on the falling edge of TCLK. 8.2.9 for more information. output drivers disabled (high impedance) output drivers enabled 19 of 130 DS32506/DS32508/DS32512 (IFSEL = 000 and LMn[1:0] and TPOS and TNEG pins, and the B3ZS/HDB3 TDAT ...
Page 20
... RCLK. and RNEG/RLCV update on the rising edge of RCLK. (RXPn/RXNn high impedance. RCLKn, RPOSn/RDATn, and high impedance.) ≠ 000). See Section 8. 130 DS32506/DS32508/DS32512 and RNEG pins, and the B3ZS/HDB3 pin, and the B3ZS/HDB3 encoder is 8.3.2 for more ≠ 000). See Section (IFSEL ...
Page 21
... See Section 8.8.3. = 11X) the upper and lower bytes can be swapped by pulling the RST = 0. See Section 8.8. INT is driven high when inactive See Section 8.10 130 DS32506/DS32508/DS32512 is asserted to access internal registers while R/W determines the type of bus transaction, (IFSEL = 10X). (IFSEL = 11X). ...
Page 22
... Synthesize the DS3, E3, and STS-1 clocks from the clock on the 1 = Source the DS3, E3, and STS-1 clocks from the CLKA, FUNCTION Table 7-6. GPIOAn pin description in Table GPIOBn pin description in Table FUNCTION ≠ 000), CLADBYP should be wired low to (IFSEL 22 of 130 DS32506/DS32508/DS32512 7-6. 7-6. REFCLK pin. CLKB and CLKC pins. ...
Page 23
... CVDD P CLAD 1.8V ±5% CVSS P CLAD Ground Table 7-11. Manufacturing Test Pin Descriptions NAME TYPE Manufacturing Test Pins MT[0] and MT[2:10] must not be connected. MT[1] MT[10:0] Test must be connected to digital ground (same as VSS pins). DS32506/DS32508/DS32512 FUNCTION FUNCTION FUNCTION 23 of 130 JTRST pin is low. JTRST can be driven ...
Page 24
... PORT.CR2:TBIN configuration bit. In TPOS = 1, while negative-polarity pulses are indicated by are high at the same time the transmitter generates an AMI pulse that is the TBIN pin high (all ports) or set the PORT.CR2:TBIN configuration bit 24 of 130 DS32506/DS32508/DS32512 TCLK is the transmit line clock and must be TPOS and ...
Page 25
... TLBO pin or the LIU.CR1:TLBO configuration bit should be high to (TXP and TXN outputs high impedance) by deasserting the Figure 4-1 shows the arrangement of the transformer when the internal 25 of 130 DS32506/DS32508/DS32512 TAIS pin or the PORT.CR3:TAIS (LMn[1:0] Figure 8-1 and Table 8-2 show the DS3 LIU.TWSCR1 and LIU ...
Page 26
... P-P 100Hz to 800kHz P-P 12kHz to 400kHz RMS 12kHz to 400kHz P-P 1-1. See Figure 8- 130 DS32506/DS32508/DS32512 and V TXMIN TDM pin and/or the TDM TDM pin and/or the TDM status bit. Shorts TDM pin and/or the TDM status bit, but , then a transmit failure alarm is SS TXP and ...
Page 27
... An isolated pulse (preceded by two zeros and followed by one zero) falls within the curves listed in Between -1.8dBm and +5.7dBm At least 20dB less than the power at 22.368MHz Ratio of positive and negative pulses must be between 0.90 and 1. 130 DS32506/DS32508/DS32512 DS325xx waveshape segments. See the LIU.TWSCR register descriptions. 0.75 1 ...
Page 28
... At the end 450ft of coaxial cable 75 Ω ( ± 1%) resistive 0.800V nominal (not covered in specs) An isolated pulse (preceded by two zeros and followed by one zero) falls within the curved listed in Between -1.8dBm and +5.7dBm At least 20dB less than the power at 25.92MHz 28 of 130 DS32506/DS32508/DS32512 register 1.0 1.25 1.5 SPECIFICATION Table 8-4. ...
Page 29
... Coaxial cable (AT&T 734A or equivalent) At the transmitter 75 Ω ( ± 1%) resistive 1.0V (nominal) An isolated pulse (preceded by two zeros and followed by one or more zeros) falls within the template shown in 0.95 to 1.05 0. 130 DS32506/DS32508/DS32512 DS325xx waveshape Zero Level segments. See the LIU.TWSCR register descriptions. Nominal Pulse 10 15 Figure 8-3 ...
Page 30
... SMT 0°C to +70°C 6 SMT SMD/A 0°C to +70°C 6 DIP DIP/A 6 SMT SMD/A 6 DIP DIP/A pin is high or the LIU.CR2:RMON configuration bit is set, the receiver can 30 of 130 DS32506/DS32508/DS32512 Figure 4-2 Table OCL L L BANDWIDTH PRIMARY (μH) 75Ω (MHz) (μ ...
Page 31
... RLOS. (192 meets the 10 ≤ N ≤ 255 pulse-interval duration requirement of G.775.) register plus 14dB. RLOS pin and the LINE.RSR:LOS status bit. During ALOS the RLOS pin (if the hardware interface is enabled) and the RLOS pin and the LOS status bit are deasserted when the DLOS condition 130 DS32506/DS32508/DS32512 8.7.1 for RCLK ...
Page 32
... PORT.CR2:RBIN configuration bit. In register. RBIN pin high (all ports) or set the PORT.CR2:RBIN configuration bit pin, while bipolar violations, code violations, and excessive zero errors are pin. register. RLCV is asserted during any 32 of 130 DS32506/DS32508/DS32512 RNEG = 1. LINE.RBPVCR register. RCLK cycle where the RPOS ...
Page 33
... RXP/RXN DD RXP Figure 4-1 RXP and RXN. To detect a type 2 failure, the receiver connects and measures the impedance between 33 of 130 DS32506/DS32508/DS32512 RCLK cycle where the data on RPD pin (all ports) or the and RXN pins become high impedance. differential inputs. By default, the receiver ...
Page 34
... Frequency (Hz) 21.9 600 2.3k 100 669 1k Frequency (Hz 130 DS32506/DS32508/DS32512 Figure 8-5 for DS3 jitter tolerance GR-253 (STS-1) G.823 (E3) DS325xx Jitter Tolerance 20k 800k 10k 100k 1M G.824 (DS3) GR-499 Cat I (DS3) GR-499 Cat II (DS3) DS325xx Jitter Tolerance 22.3k 30k 60k 300k ...
Page 35
... Table 1-1. 0.032 - (IFSEL = 000 and pins are ignored, and the LIU.CR1:JAS[1:0] and JAD[1:0] configuration 35 of 130 DS32506/DS32508/DS32512 DS325xx Wander Tolerance G.824 (DS3) G.823 (E3) 0.13 1.675 4 Frequency (Hz) HW ...
Page 36
... CATEGORY I STS- 1 [GR - 253 (1999)] CATEGORY II E3 [TBR24 (1997)] DS3 [GR - 499 (1999)] 10k 100 1k FREQUENCY (Hz) pins are the data source for the pattern detector. See 36 of 130 DS32506/DS32508/DS32512 >150k DS325xx TYPICAL RECEIVER JITTER TRANSFER WITH JITTER ATTENUATOR DISABLED CATEGORY II 100k 1M Figure 2-1 ...
Page 37
... BERT.SR register, which contains the Bit-Error Count (BEC) bit and the 8.7.4 for more details about performance monitor updates 130 DS32506/DS32508/DS32512 BERT.CR BERT.SPR2 BERT.SPR1 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF BERT ...
Page 38
... Manual Pattern Resynchronization bit (BERT.CR:MPR). The incoming data stream can be inverted before comparison with the receive pattern generator by setting BERT.CR:RPIC. See Figure 8-9 for the repetitive pattern synchronization state diagram. DS32506/DS32508/DS32512 Figure 8-8 for the PRBS synchronization diagram. Load 38 of 130 ...
Page 39
... For PRBS and QRSS patterns, the feedback is forced to one if bits 1 through 31 are all zeros. When a new pattern is loaded, the pattern generator is loaded with a seed/pattern value before pattern generation starts. The seed/pattern value is programmable ( The generated pattern can be inverted by setting BERT.CR:TPIC. DS32506/DS32508/DS32512 Match n y ...
Page 40
... When CLAD[6:4] = 000, all PLLs in the CLAD are REFCLK pin is ignored. In this mode the CLKA, CLKB, and pin high. When CLAD[6:4] ≠ 000, the PLL circuits are CLADBYP GLOBAL.SRL provides activity status for the 40 of 130 DS32506/DS32508/DS32512 n bits. The value of (IFSEL PORT.CR3 register. RXP/RXN is ignored. ...
Page 41
... Port 3 TCLK Port 4 TCLK Port 5 TCLK Port 6 TCLK Port 7 TCLK Port 8 TCLK Port 9 TCLK Port 10 TCLK Port 11 TCLK Port 12 TCLK 41 of 130 DS32506/DS32508/DS32512 CLKC CLKD Low output 77.76 or 19.44MHz output 77.76 or 19.44MHz output 77.76 or 19.44MHz output 77.76 or 19.44MHz output 77.76 or 19.44MHz output 77.76 or 19.44MHz output 77.76 or 19.44MHz output ...
Page 42
... PMS bit is set shortly after the signal goes high, and cleared shortly after the signal ≠ 000), there are two general-purpose I/O (GPIO) pins (IFSEL GLOBAL.GIOACR CONTROL BIT — GLOBAL.CR1.GPM[1:0] GLOBAL.CR1.MEIMS GLOBAL.CR1.G1SROE — 130 DS32506/DS32508/DS32512 and GLOBAL.GIOBCR registers GLOBAL.GIOARR or ...
Page 43
... For ALE high and wire A[10:0] and D[7:0] to the appropriate pins on the processor. ALE pin to the appropriate pin on the processor. For nonmultiplexed 16-bit D[15:0] to the appropriate pins on the processor 130 DS32506/DS32508/DS32512 (IFSEL = 11X), the BSWAP WR performs a write cycle. DS when ...
Page 44
... CS 8-11. After goes low, the bus master transmits a read control word with CS goes low, the bus master transmits a write control word with BURST = 130 DS32506/DS32508/DS32512 CS , SCLK, SDI, and SCLK SDO pin. SDO ...
Page 45
... To support SDI/SDO line when the DS325xx is transmitting. for AC timing specifications for the SPI interface. MSB CLOCK EDGE USED FOR DATA CAPTURE (ALL MODES 130 DS32506/DS32508/DS32512 SCLK edge that latches the LSB of a data LSB ...
Page 46
... Note: Disabling the interrupt at the block, port, or global level disables all interrupts sources at or below that level. Data Byte 0 (single-byte) 0 (single-byte) Data Byte Data Byte N 1 (burst) 1 (burst) Data Byte 1 Data Byte 130 DS32506/DS32508/DS32512 ...
Page 47
... HW = 1), the device is can be reset via the TPD ≠ 000), the device presents a number of reset and power down (IFSEL pin is active 130 DS32506/DS32508/DS32512 AND INTERRUPT GLOBAL.ISR bit GLOBAL.ISRIE bit GLOBAL.ISRIE bit INT* GLOBAL.ISR bit pin, while the receivers of all ports can be ...
Page 48
... GPIOBn) are forced to be inputs until after the TXP and TXN are forced into a high-impedance state 130 DS32506/DS32508/DS32512 INTERNAL SIGNALS Tx Port Rx Port Port Data Port Power- Power- Reset Down Down Reset ...
Page 49
... When a microprocessor interface is enabled accessible. The overall memory map is shown in of 000 to 7FFh. On the DS32508, writes in the address space for LIUs 9 through 12 are ignored, and reads from these addresses return 00h. On the DS32506, address line A[10] is not present, and writes into the address space for LIU 7 are ignored, and reads from these addresses return 00h ...
Page 50
... B3ZS/HDB3 Encoder Registers 40h–4Fh B3ZS/HDB3 Decoder Registers 50h–6Fh BERT Registers 70h–7Fh Unused Note: The address offsets given in this table are offsets from port base addresses shown in for Port 1 BLOCK PORT LIU LINE Tx LINE Rx BERT — 130 DS32506/DS32508/DS32512 Table 9-1. ...
Page 51
... Global Status Register Global Status Register Latched Global Status Register Interrupt Enable Unused General-Purpose I/O A Read Register General-Purpose I/O B Read Register Unused GLOBAL.IDR ID Register 000h ID13 ID12 ID11 5 4 ID5 ID4 ID3 51 of 130 DS32506/DS32508/DS32512 10 9 ID10 ID9 ID2 ID1 8 ID8 0 ID0 ...
Page 52
... Global PM update using the GLOBAL.CR1:GPMU bit 01 = Global PM update using the GPIOB1 pin 1X = One-second PM update using the internal one-second counter (see Section 8.7.2) GLOBAL.CR1 Global Control Register #1 002h — GPM[1:0] GPMU 130 DS32506/DS32508/DS32512 10 9 G1SRS[3: — RSTDP G1SROE 0 0 ...
Page 53
... RST bit), on all of the ports, are reset to their default state. This bit must be set high for a minimum of 100ns. This bit is logically ORed with the inverted hardware signal 0 = Normal operation 1 = Force all internal registers to their default values DS32506/DS32508/DS32512 RST . See Section 8.11 130 ...
Page 54
... Normal write mode 1 = Global write mode GLOBAL.CR2 Global Control Register #2 004h 13 12 CLAD[6: CLKD19 INTM RAS 0 0 and Table 8-12 in Section 8.7. 130 DS32506/DS32508/DS32512 RAD LSBCRE INT INT pin. The pin always drives low in Intel mode RDY/ACK ...
Page 55
... Bits 1, 0: General-Purpose I Select (GIOA1S[1:0]). These bits specify the function of the GPIOA1 pin Input 01 = Output LOS status for port Output logic Output logic 1 GLOBAL.GIOACR1 General-Purpose I/O A Control Register #1 010h GIOA7S[1: GIOA3S[1: 130 DS32506/DS32508/DS32512 10 9 GIOA6S[1:0] GIOA5S[1: GIOA2S[1:0] GIOA1S[1: ...
Page 56
... Bits 1, 0: General-Purpose I Select (GIOA9S[1:0]). These bits specify the function of the GPIOA9 pin Input 01 = Output LOS status for port Output logic Output logic 1 GLOBAL.GIOACR2 General-Purpose I/O A Control Register #2 012h 13 12 — — GIOA11S[1: 130 DS32506/DS32508/DS32512 — — — GIOA10S[1:0] GIOA9S[1: — ...
Page 57
... Note: If GLOBAL.CR1:MEIMS is set to 1, GPIOB2 is the global transmit manual error insertion (TMEI) input signal Input 01 = Output LOS status for port Output logic Output logic 1 GLOBAL.GIOBCR1 General-Purpose I/O B Control Register #1 014h GIOB7S[1: GIOB3S[1: 130 DS32506/DS32508/DS32512 10 9 GIOB6S[1:0] GIOB5S[1: GIOB2S[1:0] GIOB1S[1: ...
Page 58
... Bits 1, 0: General-Purpose I/O 9 Select (GIOB9S[1:0]). These bits specify the function of the GPIOB9 pin Input 01 = Output LOS status for port Output logic Output logic 1 GLOBAL.GIOBCR2 General-Purpose I/O B Control Register #2 016h 13 12 — — GIOB11S[1: 130 DS32506/DS32508/DS32512 — — — GIOB10S[1:0] GIOB9S[1: — ...
Page 59
... P11ISR 5 4 P5ISR P4ISR P3ISR GLOBAL.ISRIE Global Interrupt Status Register Interrupt Enable 022h — P12ISRIE P11ISRIE P5ISRIE P4ISRIE P3ISRIE 130 DS32506/DS32508/DS32512 10 9 P10ISR P9ISR P2ISR P1ISR 10 9 P10ISRIE P9ISRIE P2ISRIE P1ISRIE ...
Page 60
... GLOBAL.SRL Global Status Register Latched 02Ah — — — CLKBL CLKAL CLADL 60 of 130 DS32506/DS32508/DS32512 10 9 — — — — CLOL — 0 — — — CLOLL G1SREFL CLKC pin is active ...
Page 61
... GPIOA12 5 4 GPIOA6 GPIOA5 GPIOA4 GLOBAL.GIOBRR General-Purpose I/O B Read Register 03Ah — — GPIOB12 5 4 GPIOB6 GPIOB5 GPIOB4 61 of 130 DS32506/DS32508/DS32512 10 9 — — CLOLIE G1SREFIE GPIOA11 GPIOA10 GPIOA3 GPIOA2 10 9 GPIOB11 ...
Page 62
... See Section 8.7.4. REGISTER DESCRIPTION PORT.CR1 Port Control Register 80h + 00h — — — PMUM PMU TPD 130 DS32506/DS32508/DS32512 10 9 — — RPD RSTDP — RST ...
Page 63
... RST bit) of this port are reset to their default state. This bit must be set high for a minimum of 100ns. This bit is logically ORed with the inverted hardware signal 0 = Normal operation 1 = Force all internal registers to their default values (TXP and TXN become high impedance) RCLK RST and the GLOBAL.CR1:RST bit. See Section 8.11 130 DS32506/DS32508/DS32512 become high impedance) ...
Page 64
... Source transmit clock for port n from TCLK1 PORT.CR2 Port Control Register 80h + 02h — — — — ROD TBIN 0 0 TCLKn 64 of 130 DS32506/DS32508/DS32512 10 9 — — RBIN TCC — — ...
Page 65
... Line loopback (LLB) and diagnostic loopback (DLB) simultaneously 11 (LBS = 1) = Analog loopback (ALB) PORT.CR3 Port Control Register 80h + 04h — — — — AIST TAIS 130 DS32506/DS32508/DS32512 10 9 — BERTE LBS LB[1: BERTD ...
Page 66
... TCLK. and TNEG are sampled on the falling edge of TCLK. RNEG/RLCV RPOS/RDAT and RNEG/RLCV are updated on the falling edge of RCLK. and RNEG/RLCV are updated on the rising edge of RCLK 130 DS32506/DS32508/DS32512 10 9 — — — — ...
Page 67
... LDSR PORT.ISRIE Port Interrupt Status Register Interrupt Enable n * 80h + 14h — — — — — LDSRIE 130 DS32506/DS32508/DS32512 10 9 — — LIUSR BSR 10 9 — — LIUSRIE BSRIE — ...
Page 68
... PORT.SRL Port Status Register Latched n * 80h + 1Ah — — — — — — 130 DS32506/DS32508/DS32512 10 9 — — — — — — — — — — — — ...
Page 69
... PORT.SRL:PMSL bit mask the interrupt 1 = enable the interrupt PORT.SRIE Port Status Register Interrupt Enable n * 80h + 1Ch — — — — — — 130 DS32506/DS32508/DS32512 10 9 — — — — TCLKIE 0 0 PMSIE 0 ...
Page 70
... Transmit Waveshaping Control Register 1 Transmit Waveshaping Control Register 2 Status Register Status Register Latched Status Register Interrupt Enable Receive Gain Level Register — — JAD[1: TLBO TOE TTRE 130 DS32506/DS32508/DS32512 JAS[1: TRESADJ[2: ...
Page 71
... See Section 8.3.1. 000 = 75 Ω 001 = 82 Ω 010 = 90 Ω 011 = 100 Ω 100 = 68 Ω 101 = 62 Ω 110 = 56 Ω 111 = 50 Ω — — — RFL2E RMON RTRE 130 DS32506/DS32508/DS32512 — — — RRESADJ[2: ...
Page 72
... E3 Behavior normal overshoot decrease overshoot amplitude 2% increase overshoot amplitude 2% decrease pulse width by 0.15ns 72 of 130 DS32506/DS32508/DS32512 ...
Page 73
... DS3/STS-1 Behavior 00 - normal second fall time 01 - decrease second fall time amplitude 15 increase second fall time amplitude 15 decrease pulse width by 0.15ns DS32506/DS32508/DS32512 E3 Behavior normal pulse normal pulse normal pulse increase pulse width by 0.15ns ...
Page 74
... Table 11-6 and Table 11- 130 DS32506/DS32508/DS32512 — — — TWSC[19:16 ...
Page 75
... Bit 0: Analog Loss of Signal (ALOS). See Section 8.3. analog LOS (ALOS) condition has not been detected ALOS condition has been detected — — — — RPAS RFAIL1 130 DS32506/DS32508/DS32512 TDM TFAIL LOMC RFAIL2 RLOL ALOS ...
Page 76
... Bit 0: Analog Loss of Signal Change Latched (ALOSL). This bit is set when the LIU.SR:ALOS bit changes state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:ALOSIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set — JAFL JAEL RGLCL RPASL RFAIL1L 130 DS32506/DS32508/DS32512 TDML TFAILL LOMCL RFAIL2L RLOLL ALOSL ...
Page 77
... Bit 1: Receive Loss of Lock Interrupt Enable (RLOLIE). This bit is the interrupt enable for the LIU.SRL:RLOLL bit interrupt disabled 1 = interrupt enabled — JAFIE JAEIE RGLCIE RPASIE RFAIL1IE 130 DS32506/DS32508/DS32512 TDMIE TFAILIE LOMCIE RFAIL2IE RLOLIE ALOSIE ...
Page 78
... Values of 00–60h indicate receiver gain of 0dB to +24dB in 0.25dB increments. Values of F4–Fifth indicate receiver gain of -3dB to -0.25dB in 0.25dB increments. See Section 8.3. — — — RGL5 RGL4 RGL3 130 DS32506/DS32508/DS32512 — — — RGL2 RGL1 RGL0 ...
Page 79
... Block-level error insertion using the LINE.TCR:TSEI control bit 1 = Port-level or global-level error insertion as specified by PORT.CR1:MEIMS REGISTER DESCRIPTION B3ZS/HDB3 Transmit Control Register Unused — — — — TZSD EXZI 130 DS32506/DS32508/DS32512 — — — BPVI TSEI MEIMS ...
Page 80
... B3ZS/HDB3 Receive Status Register Interrupt Enable Unused B3ZS/HDB3 Receive Bipolar Violation Count Register B3ZS/HDB3 Receive Excessive Zero Count Register — — — — — E3CVE 130 DS32506/DS32508/DS32512 — — — REZSF RDZSF RZSD ...
Page 81
... EXZC 8.3. — — — ZSCDL EXZL EXZCL 130 DS32506/DS32508/DS32512 — — — — BPVC LOS — — — BPVL ...
Page 82
... Bit 0: Loss-of-Signal Interrupt Enable (LOSIE). This bit is the interrupt enable for the LINE.RSRL:LOSL status bit mask the interrupt 1 = enable the interrupt — — — ZSCDIE EXZIE EXZCIE 130 DS32506/DS32508/DS32512 — — — BPVIE BPVCIE LOSIE ...
Page 83
... Bit Excessive Zero Count (EXZ[15:0]). These 16 bits indicate the number of excessive zero conditions detected on the incoming bipolar data stream. See Section 8.3. BPV[15: BPV[7: EXZ[15: EXZ[7: 130 DS32506/DS32508/DS32512 ...
Page 84
... Receive Bit Count Register 1 Receive Bit Count Register 2 Unused Unused — — — RNPL RPIC MPR BERT.PCR register, and BSP[31:0] in the 84 of 130 DS32506/DS32508/DS32512 — — — APRD TNPL TPIC BERT.RBECR BERT.SPR registers ...
Page 85
... XOR of bit n and bit y. For a repetitive pattern the feedback is bit n. See Section 8.5.1. BERT.PCR register, and BSP[31:0] in the — PTS and the output of the pattern generator is forced to one if the next 85 of 130 DS32506/DS32508/DS32512 BERT.SPR registers PTF[4: PLF[4: ...
Page 86
... PRBS. BSP[31] is the first bit input on the receive side for a 32-bit repetitive pattern. See Section 8.5. BSP[15: BSP[7: BSP[31:24 BSP[23:16 130 DS32506/DS32508/DS32512 ...
Page 87
... PORT.CR1:MEIMS register bit — — — TEIR[2: bits is inverted, where n = TEIR[2:0]. A value 87 of 130 DS32506/DS32508/DS32512 — — — BEI TSEI MEIMS 8.7.5. ...
Page 88
... PMS — — — — — PMSL 130 DS32506/DS32508/DS32512 — — — — BEC OOS — — — BEL ...
Page 89
... Bits Bit Error Count (BEC[15:0 — — — — — PMSIE BEC[15: BEC[7: 130 DS32506/DS32508/DS32512 — — — BEIE BECIE OOSIE ...
Page 90
... BEC[23:16 BC[15: BC[7: BC[31:24 BC[23:16 130 DS32506/DS32508/DS32512 — — — ...
Page 91
... The identification register contains a 32-bit shift register and a 32-bit latched parallel output. Table 10-1 shows the identification register contents for the DS32506, DS32508, and DS32512 devices. Table 10-1. JTAG ID Code PART REVISION DS32506 Consult factory ...
Page 92
... are not production tested, but are guaranteed by SYMBOL CONDITIONS VDD18 VDD33 CVDD, JVDD, RVDD, and AVDD TVDD 130 DS32506/DS32508/DS32512 MIN TYP MAX UNITS 1.71 1.8 1.89 V 3.135 3.300 3.465 1.71 1.80 1.89 V 2.0 3 ...
Page 93
... A SYMBOL CONDITIONS DS32506 I DS32508 DD18 DS32512 DS32506 I DS32508 DD33 DS32512 DS32506 I DS32508 DDTTS18 DS32512 DS32506 I DS32508 DDTTS33 DS32512 DS32506, DS32508, I DDPD18 DS32512 DS32506, DS32508, I DDPD33 DS32512 (Note (Note (Note (inactive). ...
Page 94
... See Section 8.7.1 and V . OL(MAX) OH(MIN) . IH(MIN 130 DS32506/DS32508/DS32512 = -40°C to +85°C.) (See Figure 11-1 MIN TYP MAX 22.4 29.1 19 for more information on reference clocks ...
Page 95
... Figure 11-1. Transmitter Framer Interface Timing Diagram TCLK (NORMAL) TCLK (INVERTED TPOS/TDAT TNEG Figure 11-2. Receiver Framer Interface Timing Diagram RCLK (NORMAL) RCLK (INVERTED) t7 RPOS/RDAT RNEG/RLCV 130 DS32506/DS32508/DS32512 ...
Page 96
... Measured on the line side (i.e., the BNC connector side) of the 1:1 receive transformer (See Figure 4-1). During measurement, incoming data traffic is unframed 2 Note 4: With respect to nominal 1000mVpk signal PRBS PRBS 130 DS32506/DS32508/DS32512 = -40°C to +85°C.) MIN TYP MAX 1500 10 1000 200 -23 -25 -20 -22 -37 -39 ...
Page 97
... TLBO = 0 TXMIN ), TLBO = 1 TXMIN ), TLBO = 0 TXMAX ), TLBO = 1 TXMAX (Figure = -40°C to +85°C.) A MIN 900 0.95 0.95 ) TXMIN ) TXMAX (Figure 97 of 130 DS32506/DS32508/DS32512 TYP MAX UNITS 800 900 mVpk 600 700 mVpk 800 900 mVpk 600 700 mVpk 0.9 1.0 1.1 +5.7 dBm -20 dB 680 mVpk ...
Page 98
... Figure Active (Notes Active CS Inactive Inactive Inactive DS Inactive CS Active (Figure 11-3 to Figure 11-6), ALE should be wired high. In multiplexed bus applications 98 of 130 DS32506/DS32508/DS32512 = -40°C to +85°C.) A 11-7, Figure 11-8, Figure 11-9, and SYMBOL MIN TYP MAX t3a 65 t3b t6a ...
Page 99
... Figure 11-3. Parallel CPU Interface Intel Read Timing Diagram (Nonmultiplexed) t1 A[10: D[15:0] RDY Figure 11-4. Parallel CPU Interface Intel Write Timing Diagram (Nonmultiplexed) t1 A[10: D[15:0] RDY t2 t3a t16 t3b t2 t6a t7 t16 t6b 99 of 130 DS32506/DS32508/DS32512 t9a t4 t10 t5 t15 t18 t17 t9a t4 t10 t8 t18 t17 ...
Page 100
... Figure 11-5. Parallel CPU Interface Motorola Read Timing Diagram (Nonmultiplexed) t1 A[10:0] R D[15:0] RDY Figure 11-6. Parallel CPU Interface Motorola Write Timing Diagram (Nonmultiplexed) t1 A[10:0] R D[15:0] RDY t2 t3a t16 t3b t2 t6a t7 t16 t6b 100 of 130 DS32506/DS32508/DS32512 t9a t4 t10 t5 t15 t18 t17 t9a t4 t10 t8 t18 t17 ...
Page 101
... ALE t11 t12 A[10:0] t14 D[15:0] RDY Figure 11-8. Parallel CPU Interface Intel Write Timing Diagram (Multiplexed) t13 ALE t11 t12 A[10:0] t14 D[15:0] RDY t2 t3a t16 t3b t2 t6a t7 t16 t6b 101 of 130 DS32506/DS32508/DS32512 9b t4 t10 t5 t15 t18 t17 9b t4 t10 t8 t18 t17 ...
Page 102
... ALE t11 t12 A[10:0] t14 R D[15:0] RDY Figure 11-10. Parallel CPU Interface Motorola Write Timing Diagram (Multiplexed) t13 ALE t11 t12 A[10:0] t14 R D[15:0] RDY t2 t3a t16 t3b t2 t6a t7 t16 t6b 102 of 130 DS32506/DS32508/DS32512 9b t4 t10 t5 t15 t18 t17 9b t4 t10 t8 t18 t17 ...
Page 103
... SDO Enable Time (High Impedance to Output Active) SDO Disable Time (Output Active to High Impedance) SDO Data Valid Time SDO Data Hold Time After Update SCLK Edge Note 1: All timing is specified with 100 pF load on all SPI pins. DS32506/DS32508/DS32512 = -40°C to +85°C.) A SYMBOL MIN f ...
Page 104
... CLKH t SCLK, CLKL CPOL SUI HDI SDI SDO CPHA = SUC CYC SCLK, CPOL=0 t CLKH t SCLK, CLKL CPOL=1 t SUI SDI SDO t CLKL t CLKH CLKL t CLKH t HDI HDO 104 of 130 DS32506/DS32508/DS32512 t HDC DIS t HDO t HDC DIS ...
Page 105
... Not tested during production test. Figure 11-12. JTAG Timing Diagram JTCLK JTDI JTMS JTRST t6 JTDO JTRST = -40°C to +85°C.) A SYMBOL t1 t2/ 105 of 130 DS32506/DS32508/DS32512 MIN TYP MAX UNITS 1000 ns 50 500 100 ns ...
Page 106
... PIN ASSIGNMENTS Table 12-1. Pin Assignments Sorted by Signal Name for DS32506/DS32508/DS32512 SIGNAL BALL A0 V5 A1/LB5[1] T8 A2/LB6[1] W5 A3/LB7[1] R9 A4/LB8[1] Y4 A5/LB9[1] P9 A6/LB10[1] AA3 A7/LB11[1] T9 A8/LB12[1] AB2 A9/ITRE R10 A10 W6 AIST E7 ALE T10 CLADBYP G7 CLKA M21 CLKB M22 CLKC M19 CLKD M20 CS Y5 CVDD L18 ...
Page 107
... TVDD1 RVSS7 E11 TVDD1 RVSS8 W13 TVDD2 RVSS9 C14 TVDD2 RVSS10 Y17 TVDD2 RVSS11 E17 TVDD3 RVSS12 AB22 TVDD3 107 of 130 DS32506/DS32508/DS32512 BALL SIGNAL BALL M18 TXN7 B12 K20 TXN8 AA12 W22 TXN8 AB12 J19 TXN9 A16 V21 TXN9 B16 E21 ...
Page 108
... W8 TVSS1 TAIS7 G11 TVSS1 TAIS8 T11 TVSS2 TAIS9 G13 TVSS2 TAIS10 P12 TVSS2 TAIS11 G15 TVSS3 TAIS12 AB18 TVSS3 TBIN D7 TVSS3 108 of 130 DS32506/DS32508/DS32512 BALL SIGNAL BALL K6 VDD33 J13 N7 VDD33 K9 U4 VDD33 K14 V2 VDD33 N9 B9 VDD33 N14 D9 VDD33 P10 F9 VDD33 P13 ...
Page 109
... A4 CS IFSEL1 TLBO6 MT3 MT7 JVDD6 TXP6 MT4 MT8 JVSS6 TXP6 Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 109 of 130 DS32506/DS32508/DS32512 TXP5 JVSS5 RMON7 TXP5 TVDD5 GPIOB7 RVDD5 TVSS5 VDD18 RMON5 TVDD5 TLBO5 GPIOB5 TVSS5 JVDD5 GPIOA5 ...
Page 110
... TVDD12 TVSS10 RVSS10 GPIOA12 TXN10 RXN10 VDD18 TXN10 RXP10 TAIS12 Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 110 of 130 DS32506/DS32508/DS32512 RXN11 TXN11 TXP11 VSS RXP11 TXN11 TXP11 TDM9 TVSS11 TVDD11 TNEG9 TOE5 JVSS11 RLOS9 TOE9 RCLK3 ...
Page 111
... IFSEL1 TLBO6 MT3 MT7 JVDD6 TXP6 MT4 MT8 JVSS6 TXP6 Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 111 of 130 DS32506/DS32508/DS32512 TXP5 JVSS5 RMON7 RXN7 TXP5 TVDD5 LM7[0] RXP7 RVDD5 TVSS5 VDD18 RVDD7 RMON5 TVDD5 TLBO5 TVSS7 ...
Page 112
... TVDD12 TVSS10 RVSS10 LM12[1] TXN10 RXN10 VDD18 TXN10 RXP10 TAIS12 Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 112 of 130 DS32506/DS32508/DS32512 RXN11 TXN11 TXP11 VSS RXP11 TXN11 TXP11 TDM9 TVSS11 TVDD11 TNEG9 TOE5 JVSS11 RLOS9 TOE9 RCLK3 ...
Page 113
... A10 IFSEL2 CS A4 IFSEL1 N.C. MT3 MT7 JVDD6 TXP6 MT4 MT8 JVSS6 TXP6 Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 113 of 130 DS32506/DS32508/DS32512 TXP5 JVSS5 N.C. TXP5 TVDD5 GPIOB7 RVDD5 TVSS5 VDD18 N.C. TVDD5 N.C. GPIOB5 TVSS5 JVDD5 GPIOA5 TVDD5 TVSS5 N ...
Page 114
... TVSS12 N.C. JVSS12 TVDD12 TVSS10 RVSS10 GPIOA12 TXN10 RXN10 VDD18 TXN10 RXP10 N. Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 114 of 130 DS32506/DS32508/DS32512 RXN11 TXN11 TXP11 VSS RXP11 TXN11 TXP11 N.C. TVSS11 TVDD11 TNEG9 N.C. JVSS11 N.C. N.C. RCLK3 TPOS11 TCLK11 TNEG7 ...
Page 115
... Figure 12-4. DS32508 Pin Assignment, Hardware and Microprocessor Interfaces Left Half JVDD3 TVDD3 RCLKI B HW JVSS3 RPD C RST TXP3 TXP3 D TXN3 TXN3 JTDI E JTRST RXN3 RXP3 F TAIS1 RMON3 TVSS3 G VDD18 GPIOB1 TVSS3 H TXP1 TXP1 JVDD1 J TXN1 TXN1 TVDD1 K RXN1 RXP1 ...
Page 116
... N.C. N.C. N.C. N.C. N.C. N.C. VSS N.C. VSS VSS VSS VSS N.C. VSS VSS VSS VSS N.C. N.C. N.C. VDD18 N.C. N.C. N. Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 116 of 130 DS32506/DS32508/DS32512 N.C. N.C. N.C. VSS N.C. N.C. N.C. N.C. VSS VSS N.C. TOE5 VSS N.C. N.C. RCLK3 N.C. N.C. TNEG7 RNEG3 N.C. N.C. TOE7 RLOS3 RCLK7 TPOS7 TCLK7 TOE3 RLOS5 RPOS5 ...
Page 117
... Figure 12-5. DS32508 Pin Assignment, Hardware Interface Only Left Half JVDD3 TVDD3 RCLKI B HW JVSS3 RPD C RST TXP3 TXP3 D TXN3 TXN3 JTDI E JTRST RXN3 RXP3 F TAIS1 RMON3 TVSS3 G VDD18 LM1[0] TVSS3 H TXP1 TXP1 JVDD1 J TXN1 TXN1 TVDD1 K RXN1 RXP1 TVSS1 ...
Page 118
... N.C. N.C. N.C. N.C. N.C. N.C. VSS N.C. VSS VSS VSS VSS N.C. VSS VSS VSS VSS N.C. N.C. N.C. VDD18 N.C. N.C. N. Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 118 of 130 DS32506/DS32508/DS32512 N.C. N.C. N.C. VSS N.C. N.C. N.C. N.C. VSS VSS N.C. TOE5 VSS N.C. N.C. RCLK3 N.C. N.C. TNEG7 RNEG3 N.C. N.C. TOE7 RLOS3 RCLK7 TPOS7 TCLK7 TOE3 RLOS5 RPOS5 ...
Page 119
... Figure 12-6. DS32508 Pin Assignment, Microprocessor Interface Only Left Half JVDD3 TVDD3 N. JVSS3 N.C. C RST TXP3 TXP3 D TXN3 TXN3 JTDI E JTRST RXN3 RXP3 F N.C. N.C. TVSS3 G VDD18 GPIOB1 TVSS3 H TXP1 TXP1 JVDD1 J TXN1 TXN1 TVDD1 K RXN1 RXP1 TVSS1 L RVSS1 RESREF N.C. M JVDD2 JVSS2 ...
Page 120
... N.C. TCLK8 VSS N.C. N.C. N.C. N.C. N.C. N.C. VSS N.C. VSS VSS VSS VSS N.C. VSS VSS VSS VSS N.C. N.C. N.C. VDD18 N.C. N.C. N. Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 120 of 130 DS32506/DS32508/DS32512 N.C. N.C. N.C. VSS N.C. N.C. N.C. N.C. VSS VSS N.C. N.C. VSS N.C. N.C. RCLK3 N.C. N.C. TNEG7 RNEG3 N.C. N.C. N.C. N.C. RCLK7 TPOS7 TCLK7 N.C. N.C. RPOS5 TPOS3 VDD18 TNEG5 N ...
Page 121
... N.C. IFSEL2 CS A4 IFSEL1 TLBO6 MT3 N.C. JVDD6 TXP6 MT4 N.C. JVSS6 TXP6 Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 121 of 130 DS32506/DS32508/DS32512 TXP5 JVSS5 N.C. TXP5 TVDD5 N.C. RVDD5 TVSS5 VDD18 RMON5 TVDD5 TLBO5 GPIOB5 TVSS5 JVDD5 GPIOA5 TVDD5 TVSS5 JAD0 ...
Page 122
... RCLK4 N.C. N.C. VSS N.C. N.C. N.C. N.C. N.C. N.C. VSS N.C. VSS VSS VSS VSS N.C. VSS VSS VSS VSS N.C. N.C. N.C. VDD18 N.C. N.C. N. Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 122 of 130 DS32506/DS32508/DS32512 N.C. N.C. N.C. VSS N.C. N.C. N.C. N.C. VSS VSS N.C. TOE5 VSS N.C. N.C. RCLK3 N.C. N.C. N.C. RNEG3 N.C. N.C. N.C. RLOS3 N.C. N.C. N.C. TOE3 RLOS5 RPOS5 TPOS3 VDD18 TNEG5 ...
Page 123
... IFSEL2 N.C. N.C. IFSEL1 TLBO6 MT3 N.C. JVDD6 TXP6 MT4 N.C. JVSS6 TXP6 Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 123 of 130 DS32506/DS32508/DS32512 TXP5 JVSS5 N.C. TXP5 TVDD5 N.C. RVDD5 TVSS5 VDD18 RMON5 TVDD5 TLBO5 LM5[0] TVSS5 JVDD5 LM5[1] TVDD5 TVSS5 JAD0 TAIS5 ...
Page 124
... N.C. N.C. VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS N.C. VSS VSS VSS VSS N.C. VSS VSS VSS VSS N.C. N.C. N.C. VDD18 N.C. N.C. N. Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 124 of 130 DS32506/DS32508/DS32512 N.C. N.C. N.C. VSS N.C. N.C. N.C. N.C. VSS VSS N.C. TOE5 VSS N.C. N.C. RCLK3 N.C. N.C. N.C. RNEG3 N.C. N.C. N.C. RLOS3 N.C. N.C. N.C. TOE3 RLOS5 RPOS5 TPOS3 VDD18 TNEG5 TDM5 ...
Page 125
... WR TVDD6 D9 A2 N.C. IFSEL2 CS A4 IFSEL1 N.C. MT3 N.C. JVDD6 TXP6 MT4 N.C. JVSS6 TXP6 Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 125 of 130 DS32506/DS32508/DS32512 TXP5 JVSS5 N.C. TXP5 TVDD5 N.C. RVDD5 TVSS5 VDD18 N.C. TVDD5 N.C. GPIOB5 TVSS5 JVDD5 GPIOA5 TVDD5 TVSS5 N.C. N.C. VSS N.C. ...
Page 126
... TCLK4 TNEG2 N.C. N.C. RCLK4 N.C. N.C. VSS N.C. N.C. N.C. N.C. N.C. N.C. VSS N.C. VSS VSS VSS VSS N.C. VSS VSS VSS VSS N.C. N.C. N.C. VDD18 N.C. N.C. N. Low-Speed Analog Low-Speed Digital VDD 1.8V Analog VSS VSS 126 of 130 DS32506/DS32508/DS32512 N.C. N.C. N.C. VSS N.C. N.C. N.C. N.C. VSS VSS N.C. N.C. VSS N.C. N.C. RCLK3 N.C. N.C. N.C. RNEG3 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. RPOS5 TPOS3 VDD18 TNEG5 N.C. RPOS1 TNEG1 N.C. ...
Page 127
... PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 13.1 484-Lead BGA (23mm x 23mm) (56-G60038-001) DS32506/DS32508/DS32512 127 of 130 ...
Page 128
... The package is mounted on a four - layer JEDEC standard test board with no airflow and dissipating maximum power. Table 14-2. Theta-JA (θ ) vs. Airflow JA FORCED AIR (METERS PER THETA-JA (θ SECOND) 0 16.0 ° C/W 1 13.8 ° C/W 12.8 ° C/W 2 MIN TYP -40 -40 16.0 5.4 7.7 0 128 of 130 DS32506/DS32508/DS32512 MAX UNITS ° C +85 +125 ° C ° C/W ° C/W ° C/W ° C/W ...
Page 129
... Synchronous Transmission Signal STS-1 Synchronous Transmission Signal at Level 1 Tx, TX Transmit UI Unit Interval UI Unit Interval Peak-to-Peak P-P UI Unit Intervals Root Mean Square RMS 16. TRADEMARK ACKNOWLEDGEMENTS ACCUNET is a registered trademark of AT&T. SPI is a trademark of Motorola, Inc. Telcordia is a registered trademark of Telcordia Technologies. DS32506/DS32508/DS32512 129 of 130 ...
Page 130
... Table 12-1, added ITRE to ball R10. In Figure 12-2, Figure DS32512, DS32508, and DS32506 hardware-interface-only pin assignments. In Figure 12-8 (left half), corrected typos where some pins for port 7 were listed (do not exist on the DS32506). Changed pins A10, A11, B10, B11, F11, and G11 to N.C. 040808 Changed pins C11, D11, E11, G10, R9, and V4 to VSS. ...