DS21Q41BT+ Maxim Integrated, DS21Q41BT+ Datasheet - Page 35
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DS21Q41BT+
Manufacturer Part Number
DS21Q41BT+
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21Q41BT.pdf
(61 pages)
Specifications of DS21Q41BT+
Product
Framer
Number Of Transceivers
4
Data Rate
2.048 Mbps
Supply Current (max)
30 mA
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
TQFP-128
Minimum Operating Temperature
0 C
Operating Supply Voltage
5 V
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Part # Aliases
90-21Q41+BT0
RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address=60 to 6B Hex)
(MSB)
Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed bit signaling from eight
DS0 channels. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and
D). In the D4 framing mode, there are only two signaling bits per channel (A and B). In the D4 framing
mode, the DS21Q41B will replace the C and D signaling bit positions with the A and B signaling bits
from the previous multiframe. Hence, whether the DS21Q41B is operated in either framing mode, the
user needs only to retrieve the signaling bits every 3 ms. The bits in the Receive Signaling Registers are
updated on multiframe boundaries in both framing modes so the user can utilize the Receive Multiframe
Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the signaling bits. The
Receive Signaling Registers are frozen and not updated during a loss of sync condition (SR1.0=1). They
will contain the most recent signaling information before the “OOF” occurred.
A/C(16)
A/C(24)
B/D(16)
B/D(24)
A/C(8)
B/D(8)
A(16)
A(24)
B(16)
B(24)
A(8)
B(8)
SYMBOL
D(24)
A(1)
A/C(15)
A/C(23)
B/D(15)
B/D(23)
A/C(7)
B/D(7)
A(15)
A(23)
B(15)
B(23)
A(7)
B(7)
POSITION
A/C(14)
A/C(22)
B/D(14)
B/D(22)
A/C(6)
B/D(6)
RS12.7
A(14)
A(22)
B(14)
B(22)
RS1.0
A(6)
B(6)
A/C(13)
A/C(21)
B/D(13)
B/D(21)
A/C(5)
B/D(5)
A(13)
A(21)
B(13)
B(21)
A(5)
B(5)
NAME AND DESCRIPTION
Signaling Bit D in Channel 24
Signaling Bit A in Channel 1
A/C(12)
A/C(20)
B/D(12)
B/D(20)
35 of 61
A/C(4)
B/D(4)
A(12)
A(20)
B(12)
B(20)
A(4)
B(4)
A/C(11)
A/C(19)
B/D(11)
B/D(19)
A/C(3)
B/D(3)
A(11)
A(19)
B(11)
B(19)
A(3)
B(3)
A/C(10)
A/C(18)
B/D(10)
B/D(18)
A/C(2)
B/D(2)
A(10)
A(18)
B(10)
B(18)
A(2)
B(2)
A/C(17)
B/D(17)
A/C(1)
A/C(9)
B/D(1)
B/D(9)
A(17)
B(17)
A(1)
A(9)
B(1)
B(9)
(LSB)
RS11 (6A)
RS12 (6B)
RS10 (69)
RS1 (60)
RS2 (61)
RS3 (62)
RS4 (63)
RS5 (64)
RS6 (65)
RS7 (66)
RS8 (67)
RS9 (68)
DS21Q41B