93LC56B-I/P Microchip Technology, 93LC56B-I/P Datasheet - Page 7

• Manufacturer Part Number: 93LC56B-I/P
• Description: IC EEPROM 2KBIT 3MHZ 8DIP
• Manufacturer: Microchip Technology

Specifications of 93LC56B-I/P

• Memory Size: 2K (128 x 16)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 2MHz, 3MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 128 K x 16
• Interface Type: Microwire
• Maximum Clock Frequency: 2 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 0.5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Package: 8PDIP
• Density: 2 Kb
• Maximum Operating Frequency: 2 MHz
• Typical Operating Supply Voltage: 3.3|5 V
• Data Retention: 200(Min) Year
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 93LC56B-I/PG

2.4
The ERASE instruction forces all data bits of the speci-
fied address to the logical ‘1’ state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed program-
ming cycle, except on ‘93C’ devices where the rising
edge of CLK before the last address bit initiates the
write cycle.
FIGURE 2-1:
FIGURE 2-2:
© 2008 Microchip Technology Inc.
CLK
CLK
DO
DO
CS
DI
CS
DI
Erase
High-Z
High-Z
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
1
1
ERASE TIMING FOR 93AA AND 93LC DEVICES
ERASE TIMING FOR 93C DEVICES
1
1
1
1
A
A
N
N
A
A
N
N
-1 A
-1 A
N
N
-2
-2
•••
•••
A0
A0
The DO pin indicates the Ready/
device if CS is brought high after a minimum of 250 ns
low (T
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
Note:
T
T
CSL
CSL
CSL
). DO at logical ‘0’ indicates that programming
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/
T
WC
T
T
T
SV
WC
SV
Check Status
Check Status
Busy
Busy
Busy
status from DO.
Ready
Ready
Busy
DS21794F-page 7
High-Z
High-Z
status of the
T
T
CZ
CZ