DS1345WP-100 Maxim Integrated, DS1345WP-100 Datasheet - Page 8

• Manufacturer Part Number: DS1345WP-100
• Description: NVRAM 3.3V 1024K NV SRAM w/Battery Monitor
• Manufacturer: Maxim Integrated

Specifications of DS1345WP-100

• Data Bus Width: 8 bit
• Memory Size: 1 Mbit
• Organization: 128 K x 8
• Interface Type: Parallel
• Access Time: 100 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Operating Current: 50 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: PowerCap Module
• Mounting Style: SMD/SMT
• Part # Aliases: 90-1345W-P10

POWER-DOWN/POWER-UP TIMING
BATTERY WARNING TIMING
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
2.
3. t
4. t
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the
7. If the
8. If
9. Each DS1345W has a built-in switch that disconnects the lithium source until V
PARAMETER
V
V
V
Active
V
V
Inactive
V
Protection
V
V
PARAMETER
Battery Test Cycle
Battery Test Pulse Width
Battery Test to
PARAMETER
Expected Data
Retention Time
WE
CC
CC
CC
CC
CC
CC
CC
CC
going low to the earlier of
buffers remain in a high impedance state during this period.
buffers remain in high impedance state during this period.
the output buffers remain in a high impedance state during this period.
the user. The expected t
time power is first applied by the user.
WE
OE
WP
DS
Fail Detect to
slew from V
Fail Detect to
slew from 0V to V
Valid to
Valid to End of Write
Valid to
Valid to
Inactive
WE
is measured from the earlier of
is specified as the logical AND of
= V
is high for a read cycle.
CE
CE
is low or the
IH
or V
low transition occurs simultaneously with or latter than the
high transition occurs prior to or simultaneously with the
CE
RST
BW
BW
TP
and
IL
Valid
Inactive
CE
RST
to 0V
. If
Active
WE
and
TP
OE
WE
= V
DR
low transition occurs prior to or simultaneously with the
CE
is defined as accumulative time in the absence of V
IH
SYMBOL
SYMBOL
SYMBOL
or
during write cycle, the output buffers remain in a high impedance state.
t
WE
t
t
t
t
t
BTPW
t
t
t
t
RPD
REC
RPU
BPU
BTC
t
BW
t
CE
PD
PU
DR
F
R
going high.
or
CE
WE
and
MIN
MIN
MIN
150
150
150
going high.
10
8 of 10
WE
. t
WP
TYP
TYP
TYP
200
24
is measured from the latter of
MAX
MAX
MAX
125
350
1.5
15
2
1
1
1
WE
WE
high transition, the output
low transition, the output
(T
(T
UNITS
UNITS
UNITS
years
A
A
CC
ms
ms
ms
µs
µs
µs
µs
CC
hr
: See Note 10)
: See Note 10)
s
s
s
CE
is first applied by
starting from the
(T
low transition,
A
= +25°C)
CE
NOTES
NOTES
NOTES
DS1345W
11
14
14
14
9
or
WE