XRT83SL38ES Exar, XRT83SL38ES Datasheet - Page 14

• Manufacturer Part Number: XRT83SL38ES
• Description: Peripheral Drivers & Components - PCIs 8 CHT1/E1LIUSH
• Manufacturer: Exar

Specifications of XRT83SL38ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MICROPROCESSOR INTERFACE
S
HW_HOST
IGNAL
WR_R/W
ALE_AS
RD_DS
EQC0
EQC1
EQC2
EQC3
CS
N
AME
L
EAD
T10
D7
D7
C7
C7
A7
A7
B7
B7
#
T
YPE
I
I
I
I
I
Mode Control Input
This pin selects Hardware or Host mode. Leave this pin unconnected or tie “High” to
select Hardware mode.
For Host mode, this pin must be tied “Low”.
N
Write Input (Read/Write) - Host mode:
Intel bus timing: A “Low” pulse on WR selects a write operation when CS pin is
“Low”.
Motorola bus timing: A “High” pulse on R/W selects a read operation and a “Low”
pulse on R/W selects a write operation when CS is “Low”.
Equalizer Control Input pin 0 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and Trans-
mitter Line Build Out.
MIT LINE BUILD-OUT SETTINGS” ON PAGE 30.
N
Read Input (Data Strobe) - Host mode
Intel bus timing: A “Low” pulse on RD selects a read operation when the CS pin is
“Low”.
Motorola bus timing: A “Low” pulse on DS indicates a read or write operation when
the CS pin is “Low”.
Equalizer Control Input pin 1 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and Trans-
mitter Line Build Out.
MIT LINE BUILD-OUT SETTINGS” ON PAGE 30.
N
Address Latch Input (Address Strobe) - Host mode
Intel bus timing: The address inputs are latched into the internal register on the fall-
ing edge of ALE.
Motorola bus timing: The address inputs are latched into the internal register on the
falling edge of AS.
Equalizer Control Input pin 2 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and Trans-
mitter Line Build Out.
MIT LINE BUILD-OUT SETTINGS” ON PAGE 30.
N
Chip Select Input - Host mode:
This signal must be “Low” in order to access the parallel port.
Equalizer Control Input pin 3 - Hardware mode:
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and Trans-
mitter Line Build Out.
MIT LINE BUILD-OUT SETTINGS” ON PAGE 30.
N
OTE
OTE
OTE
OTE
OTE
: Internally pulled “High” with a 50kΩ resistor.
: Internally pulled “Low” with a 50kΩ resistor.
: Internally pulled “Low” with a 50kΩ resistor.
: Internally pulled “Low” with a 50kΩ resistor.
: Internally pulled “Low” with a 50kΩ resistor.
SEE”RECEIVE EQUALIZER CONTROL AND TRANS-
SEE”RECEIVE EQUALIZER CONTROL AND TRANS-
SEE”RECEIVE EQUALIZER CONTROL AND TRANS-
SEE”RECEIVE EQUALIZER CONTROL AND TRANS-
12
D
ESCRIPTION
REV. 1.0.2