XRT83SL28ES Exar, XRT83SL28ES Datasheet - Page 18

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XRT83SL28ES

Manufacturer Part Number
XRT83SL28ES
Description
Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH
Manufacturer
Exar
Datasheet

Specifications of XRT83SL28ES

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
N
To meet short haul requirements, the XRT83SL28 can accept E1 signals that have been attenuated by 9dB of
cable loss in E1 mode. The test configuration for measuring the receive sensitivity is shown in Figure 8.
F
The receive path detects RLOS and AIS. These alarms can be individually masked to prevent the alarm from
triggering an interrupt. To enable interrupt generation, the Global Interrupt Enable (GIE) bit must be set "High"
in the appropriate global register. Any time a change in status occurs (if the alarms are enabled), the interrupt
pin will pull "Low" to indicate an alarm has occurred. Once the status registers have been read, the INT pin will
return "High". The status registers are Reset Upon Read (RUR).
N
1.4
1.5
OTE
IGURE
OTE
RCLK Rise Time (10% to 90%)
RCLK Fall Time (90% to 10%)
: VDD=3.3V ±5%, T
: The interrupt pin is an Open-Drain output that requires a 10kΩ pull-up resistor.
with 25pF Loading
with 25pF Loading
8. T
Receive Sensitivity
General Alarm Detection and Interrupt Generation
P
ARAMETER
EST
E1 = PRBS 2
C
W&G ANT20
ONFIGURATION FOR
Analyzer
Network
A
15
=25°C, Unless Otherwise Specified
- 1
T
ABLE
Tx
Rx
2: T
S
RCLK
RCLK
IMING
M
YMBOL
EASURING
R
F
S
Cable Loss
PECIFICATIONS FOR
R
ECEIVE
M
16
-
-
IN
S
ENSITIVITY
Rx
Tx
RCLK/RPOS/RNEG
T
Short Haul LIU
YP
-
-
XRT83SL28
8-Channel
External Loopback
M
40
40
AX
xr
U
REV. 1.0.0
NITS
ns
ns

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