24LC04BHT-I/MNY Microchip Technology, 24LC04BHT-I/MNY Datasheet - Page 9

• Manufacturer Part Number: 24LC04BHT-I/MNY
• Description: IC EEPROM 4KBIT 400KHZ 8TDFN
• Manufacturer: Microchip Technology

Specifications of 24LC04BHT-I/MNY

• Memory Size: 4K (2 x 256 x 8)
• Package / Case: 8-TDFN
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Organization: 2 Block x 256 x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 24LC04BHT-I/MNYTR

7.0
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘
of read operations: current address read, random read
and sequential read.
7.1
The 24XX04H contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘
(either a read or write operation) was to address
next current address read operation would access data
from address
with R/W bit set to ‘
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer, but does generate a Stop
condition and the 24XX04H discontinues transmission
(Figure 7-1).
7.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX04H as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again, but with the R/W bit set to a ‘
The 24XX04H will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition and the 24XX04H will discontinue transmis-
sion (Figure 7-2).
FIGURE 7-1:
© 2008 Microchip Technology Inc.
READ OPERATION
Current Address Read
Random Read
n + 1
x = “don’t care”
Bus Activity
Master
SDA Line
Bus Activity
1
’. Therefore, if the previous access
1
’, the 24XX04H issues an acknowl-
. Upon receipt of the slave address
CURRENT ADDRESS READ
1
’. There are three basic types
S
T
A
R
T
S
1 0 1 0 x x B0 1
n
Control
, the
Byte
1
’.
Select
Block
Bits
7.3
Sequential reads are initiated in the same way as a
random read, except that once the 24XX04H transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24XX04H to transmit the next sequentially-
addressed 8-bit word (Figure 7-3).
To provide sequential reads, the 24XX04H contains an
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
7.4
The 24XX04H employs a V
which disables the internal erase/write logic if the V
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
24AA04H/24LC04BH
A
C
K
Sequential Read
Noise Protection
Data (n)
CC
threshold detector circuit
N
o
A
C
K
P
S
T
O
P
DS22119A-page 9
CC