MAX8741EAI-T Maxim Integrated, MAX8741EAI-T Datasheet - Page 19
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MAX8741EAI-T
Manufacturer Part Number
MAX8741EAI-T
Description
Current & Power Monitors & Regulators
Manufacturer
Maxim Integrated
Datasheet
1.MAX8741EAI.pdf
(34 pages)
current to reverse at light loads. This results in fixed-fre-
quency operation and continuous inductor-current flow.
This eliminates discontinuous-mode inductor ringing
and improves cross-regulation of transformer-coupled
multiple-output supplies, particularly in circuits that do
not use additional secondary regulation through SECFB
or V
In most applications, connect SKIP to GND to minimize
quiescent supply current. V
high is typically 30mA, depending on external MOSFET
gate capacitance and switching losses.
Soft-start allows a gradual increase of the internal cur-
rent-limit level at startup to reduce input surge currents.
Both SMPSs contain internal digital soft-start circuits,
each controlled by a counter, a digital-to-analog con-
verter (DAC), and a current-limit comparator. In shut-
down or standby mode, the soft-start counter is reset to
zero. When an SMPS is enabled, its counter starts
counting oscillator pulses, and the DAC begins incre-
menting the comparison voltage applied to the current-
limit comparator. The DAC output increases from 0 to
100mV in five equal steps as the count increases to
512 clocks. As a result, the main output capacitor
charges up relatively slowly. The exact time of the out-
put rise depends on output capacitance and load cur-
rent, and is typically 600µs with a 500kHz oscillator.
Dropout (low input-output differential operation) is
enhanced by stretching the clock pulse width to
increase the maximum duty factor. The algorithm fol-
lows: if the output voltage (V
tion without the current limit having been reached, the
SMPS skips an off-time period (extending the on-time).
At the end of the cycle, if the output is still out of regula-
tion, the SMPS skips another off-time period. This
action can continue until three off-time periods are
skipped, effectively dividing the clock frequency by as
much as four.
The typical PWM minimum off-time is 300ns, regardless
of the operating frequency. Lowering the operating fre-
quency raises the maximum duty factor above 97%.
Fixed, preset output voltages are selected when FB_ is
connected to ground. Adjusting the main output volt-
age with external resistors is simple for any of the
MAX8741/MAX8742, through resistor-dividers connect-
500kHz Multi-Output Power-Supply Controllers
DD
.
Internal Digital Soft-Start Circuit
______________________________________________________________________________________
Adjustable-Output Feedback
L
OUT
supply current with SKIP
Dropout Operation
with High Impedance in Shutdown
) drops out of regula-
(Dual-Mode FB)
ed to FB3 and FB5 (Figure 2). Calculate the output volt-
age with the following formula:
where V
The nominal output should be set approximately 1% or
2% high to make up for the MAX8741/MAX8742 -2% typ-
ical load-regulation error. For example, if designing for a
3.0V output, use a resistor ratio that results in a nominal
output voltage of 3.05V. This slight offsetting gives the
best possible accuracy. Recommended normal values
for R2 range from 5kΩ to 100kΩ. To achieve a 2.5V nom-
inal output, connect FB_ directly to CSL_.
Remote output-voltage sensing, while not possible in
fixed-output mode due to the combined nature of the
voltage-sense and current-sense inputs (CSL3 and
CSL5), is easy to do in adjustable mode by using the top
of the external resistor-divider as the remote sense point.
When using adjustable mode, it is a good idea to
always set the “3.3V output” to a lower voltage than the
“5V output.” The 3.3V output must always be less than
V
common-mode range of the current-sense inputs. While
V
ly regulating, and as low as 4.2V when automatically
bootstrapped to CSH5.
A flyback-winding control loop regulates a secondary
winding output, improving cross-regulation when the
primary output is lightly loaded or when there is a low
input-output differential voltage. If V
below its regulation threshold, the low-side switch is
turned on for an extra 0.75µs. This reverses the induc-
tor (primary) current, pulling current from the output fil-
ter capacitor and causing the flyback transformer to
operate in forward mode. The low impedance present-
ed by the transformer secondary in forward mode
dumps current into the secondary output, charging up
the secondary capacitor and bringing V
back into regulation. The secondary feedback loop
does not improve secondary output accuracy in normal
flyback mode, where the main (primary) output is heavi-
ly loaded. In this condition, secondary output accuracy
is determined by the secondary rectifier drop, trans-
former turns ratio, and accuracy of the main output
L
L
, so that the voltage on CSH3 and CSL3 is within the
is nominally 5V, it can be as low as 4.7V when linear-
Secondary Feedback Regulation Loop
REF
= 2.5V nominal.
V
OUT
= V
REF
(1 + R1 / R2)
(SECFB or V
DD
or SECFB falls
DD
or SECFB
DD
19
)