MAX1808EUB+ Maxim Integrated, MAX1808EUB+ Datasheet - Page 15

• Manufacturer Part Number: MAX1808EUB+
• Description: Current & Power Monitors & Regulators
• Manufacturer: Maxim Integrated

requirements. Choose the small-signal components for
the error amplifier to achieve the desired closed-loop
bandwidth and phase margin.
To choose the appropriate compensation network type,
the power-supply poles and zeros, the zero crossover
frequency, and the type of the output capacitor must be
determined.
In a buck converter, the LC filter in the output stage intro-
duces a pair of complex poles at the following frequency:
The output capacitor introduces a zero at:
where ESR is the equivalent series resistance of the
output capacitor.
The loop-gain crossover frequency (f
gain equals 1 (0dB) should be set below 1/10th of the
switching frequency:
Choosing a lower crossover frequency reduces the
effects of noise pick-up into the feedback loop, such as
jittery duty cycle.
To maintain a stable system, two stability criteria must
be met:
1) The phase shift at the crossover frequency f
2) The gain at the frequency where the phase shift is
Maintain a phase margin of around 60° to achieve a
robust loop stability and well-behaved transient
response.
When using an electrolytic or large-ESR tantalum output
capacitor the capacitor ESR zero f
between the LC poles and the crossover frequency f
(f
gral) compensation network.
When using a ceramic or low-ESR tantalum output
capacitor, the capacitor ESR zero typically occurs
above the desired crossover frequency f
f
and derivative) compensation network.
Maxim Integrated
O
PO
< f
be less than 180°. In other words, the phase margin
of the loop must be greater than zero.
-180° (gain margin) must be less than 1.
< f
ZO
Low-Cost, Small, 4.5V to 28V Wide Operating
ZO
. Choose Type III (PID—proportional, integral,
Range, DC-DC Synchronous Buck Controller
< f
O
f
). Choose Type II (PI—proportional-inte-
PO
f
ZO
=
=
2π
2π
f
×
O
×
≤
L
ESR C
OUT
f
SW
10
1
1
×
×
C
OUT
OUT
ZO
O
), where the loop
typically occurs
O
, that is f
O
, must
PO
O
<
If f
of the capacitor ESR zero almost cancels the phase
loss of one of the complex poles of the LC filter around
the crossover frequency. Use a Type II compensation
network with a midband zero and a high-frequency
pole to stabilize the loop. In Figure 3, R
duce a midband zero (f
compensation network provide a high-frequency pole
(f
quency ripple.
Follow the instructions below to calculate the component
values for the Type II compensation network in Figure 3:
1) Calculate the gain of the modulator (GAIN
where V
the amplitude of the ramp in the pulse-width modulator,
V
see the Electrical Characteristics table), and V
the desired output voltage.
The gain of the error amplifier (GAIN
quencies is:
where g
The total loop gain, which is the product of the modula-
tor gain and the error amplifier gain at f
So:
Solving for R
2) Set a midband zero (f
P1
FB
ZO
comprised of the regulator’s pulse-width modulator,
LC filter, feedback divider, and associated circuitry
at the crossover frequency:
one of the LC poles):
), which mitigates the effects of the output high-fre-
is the FB input voltage set-point (0.591V typically,
GAIN
V
is lower than f
RAMP
V
IN
M
IN
R
is the transconductance of the error amplifier.
MOD
F
is the input voltage of the regulator, V
=
×
F
f
Z
:
(
V
1
2
RAMP
Type II Compensation Network
=
π
GAIN
=
V
×
2
GAIN
RAMP
V
f
π
O
ESR
O
IN
V
×
×
MOD
FB
×
and close to f
(
R
L
2π
1
EA
F
Z1
×
×
OUT
×
V
(
×
Z1
). R
×
= g
IN
2π
C
GAIN
f
O
) at 0.75 x f
)
F
MAX15026
×
F
×
×
M
×
g
=
f
V
and C
ESR
O
L
M
x R
V
0 75
EA
OUT
OUT
FB
.
×
×
F
L
ESR
PO
EA
= 1
OUT
×
)
×
CF
O
) in midband fre-
, the phase lead
×
f
g
PO
, is 1.
F
M
V
PO
)
in the Type II
OUT
and C
×
×
(Figure 3)
R
V
(to cancel
V
OUT
F
FB
RAMP
=
F
OUT
MOD
1
intro-
15
is
is
),