MAX1808EUB+ Maxim Integrated, MAX1808EUB+ Datasheet - Page 7

• Manufacturer Part Number: MAX1808EUB+
• Description: Current & Power Monitors & Regulators
• Manufacturer: Maxim Integrated

Maxim Integrated
PIN
10
11
12
13
14
—
1
2
3
4
5
6
7
8
9
Low-Cost, Small, 4.5V to 28V Wide Operating
Range, DC-DC Synchronous Buck Controller
PGOOD
NAME
COMP
GND
DRV
V
BST
LIM
DH
EN
DL
FB
RT
LX
EP
IN
CC
Regulator Input. Bypass IN to GND with a 1µF minimum ceramic capacitor. Connect IN to V
operating in the 5V ±10% range.
5.25V Linear Regulator Output. Bypass V
capacitor to ensure stability up to the regulated rated current when V
DRV. Bypass V
minimum ceramic capacitor.
Open-Drain Power-Good Output. Connect PGOOD with an external resistor to any supply voltage.
Active-High Enable Input. Pull EN to GND to disable the output. Connect EN to V
operation. EN can be used for power sequencing and as a UVLO adjustment input.
Current-Limit Adjustment. Connect a resistor from LIM to GND to adjust current-limit threshold from
30mV (R
Compensation Input. Connect compensation network from COMP to FB or from COMP to GND. See
the Compensation section.
Feedback Input. Connect FB to a resistive divider between output and GND to adjust the output
voltage between 0.6V and (0.85 x Input Voltage). See the Setting the Output Voltage section.
Oscillator Timing Resistor Input. Connect a resistor from RT to GND to set the oscillator frequency
from 200kHz to 2MHz. See the Setting the Switching Frequency section.
Ground
Drive Supply Voltage. DRV is internally connected to the anode terminal of the internal boost diode.
Bypass DRV to GND with a 2.2µF minimum ceramic capacitor (see the Typical Application Circuits).
Low-Side Gate-Driver Output. DL swings from DRV to GND. DL is low during UVLO.
Boost Flying Capacitor. Connect a ceramic capacitor with a minimum value of 100nF between BST
and LX.
External Inductor Connection. Connect LX to the switching side of the inductor. LX serves as the
lower supply rail for the high-side gate driver and as a sensing input of the drain to source voltage
drop of the synchronous MOSFET.
High-Side Gate-Driver Output. DH swings from LX to BST. DH is low during UVLO.
Exposed Pad. Internally connected to GND. Connect EP to a large copper plane at GND potential to
improve thermal dissipation. Do not use EP as the only GND ground connection.
LIM
= 6kΩ) to 300mV (R
CC
to GND when V
LIM
CC
= 60kΩ). See the Setting the Valley Current Limit section.
supplies the device core quiescent current with a 2.2µF
CC
to GND with a minimum of 4.7µF low-ESR ceramic
FUNCTION
CC
MAX15026
supplies the drive current at
Pin Description
CC
for always-on
CC
when
7