MAX5942BCSE Maxim Integrated, MAX5942BCSE Datasheet - Page 10

• Manufacturer Part Number: MAX5942BCSE
• Description: Power Switch ICs - POE / LAN
• Manufacturer: Maxim Integrated

IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
10
PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
______________________________________________________________________________________
SS_SHDN
PGOOD
PGOOD
NAME
NDRV
UVLO
GATE
GND
OUT
V
RCL
V
V
V+
CS
FB
V-
DD
CC
EE
H i g h- V ol tag e S tar tup Inp ut. Refer enced to V - . C onnect d i r ectl y to an i np ut vol tag e r ang e b etw een 18V to 67V .
C onnects i nter nal l y to a hi g h- vol tag e l i near r eg ul ator that g ener ates V
Line Regulator Input. Referenced to V-. V
supply voltages less than 36V, connect V
V
Bypass V
Fixed-Gain Inverting Amplifier Input. Referenced to V-. Connect a voltage-divider from the regulated output
to FB. The noninverting input of the amplifier is referenced to +2.4V
Soft-Start Timing Capacitor Connection. Referenced to V-. Ramp time to full current limit is approximately
0.45ms/nF. Bypass with a minimum 10nF capacitor to V-. A 2.4V reference voltage appears across the
capacitor. Disable the PWM controller by pulling SS_SHDN below 0.25V.
Undervoltage Lockout Programming Input for Power Mode. Referenced to V
threshold, the device enters the power mode. Connect UVLO to V
threshold. Connect UVLO to an external resistor-divider to define a threshold externally. The series
resistance value of the external resistors must add to 25.5kΩ (±1%) and replaces the detection resistor. To
keep the device in undervoltage lockout, pull UVLO between V
Classification Setting. Referenced to V
Gate of Internal N-Channel Power MOSFET. Referenced to V
enters the power mode. Connect an external 100V ceramic capacitor from GATE to V
inrush current. Pull GATE to V
operate normally when GATE is pulled to V
N e g a t i v e I n p u t P o w e r . S o u r ce o f th e i n te g r a t ed i s o l a t i o n N - c h a nn e l p ow e r M O S F E T . C o n n e ct V
- 4 8V .
Output Voltage. Referenced to V
OUT to V-.
Power-Good Indicator Output, Active High, Open Drain. PGOOD is referenced to OUT. PGOOD goes high
impedance when V
to OUT (given that V
Power-Good Indicator Output, Active Low, Open Drain. PGOOD is referenced to V
V
impedance.
Ground. Referenced to V
Current-Sense Input. Referenced to V-. Turns power switch off if V
current limiting. CS is also the feedback for the current-mode controller. CS connects to the PWM controller
through a leading-edge blanking circuit.
Ground. V- is the ground terminal of the PWM controller.
Gate Drive. Referenced to V-. Drives a high-voltage external N-channel power MOSFET.
Regulated IC Supply. Referenced to V-. Provides power for MAX5942_. V
normal operation and from V+ during startup. Bypass V
0.1µF ceramic capacitor to V-.
DD
EE
when V
receives its power from the tertiary winding of the transformer and accepts voltages from 13V to 36V.
DD
OUT
to V- with a 4.7µF capacitor.
is within 1.2V of V
OUT
OUT
is within 1.2V of V
is at least 5V below GND).
EE
. GND is the positive input power.
EE
EE
to turn off the internal MOSFET. The detection and classification functions
EE
. Drain of the integrated isolation N-channel power MOSFET. Connect
and when GATE is 5V above V
EE
. Add a resistor from RCL to V
DD
DD
EE
EE
is the input to the linear regulator that generates V
and when GATE is 5V above V
and V+ to the supply. For supply voltages greater than 36V,
.
FUNCTION
CC
with a 10µF tantalum capacitor in parallel with a
EE .
TH,G,UVLO
C C
GATE sources 10µA when the device
EE
CS
d ur i ng star tup .
EE
to use the default undervoltage lockout
rises above 465mV for cycle-by-cycle
. Otherwise, PGOOD goes high
EE
CC
and V
to set a PD class (see Table 1).
EE
EE
is regulated from V
. Otherwise, PGOOD is pulled
. When UVLO is above its
REF,UVLO
Pin Description
EE
. PGOOD is pulled to
OUT
.
to program the
CC
DD
. For
during
E E
t o