NCP4303AMNTWG ON Semiconductor, NCP4303AMNTWG Datasheet - Page 23

• Manufacturer Part Number: NCP4303AMNTWG
• Description: Power Switch ICs - Power Distribution SEC SIDE SYNC RECT DRV
• Manufacturer: ON Semiconductor

Specifications of NCP4303AMNTWG

• Product Category: Power Switch ICs - Power Distribution

a way that the maximum pulse current into the Min_Toff
adjust pin is below 10 mA. Voltage on the min T
pins is clamped by internal zener protection to 10 V.
Power Dissipation Calculation
MOSFET driver of a SR system. If no external gate resistor
is used and the internal gate resistance of the MOSFET is
very low, nearly all energy losses related to gate charge are
dissipated in the driver. Thus it is necessary to check the SR
driver power losses in the target application to avoid over
temperature and to optimize efficiency.
conducting before turn on because the V
level is below 0 V. On the other hand, the SR MOSFET turn
in ZVS mode is given by the parallel combination of the gate
to source and gate to drain capacitances (i.e. C
for given gate to source voltage). The total gate charge,
Q
switching conditions. In order to accurately calculate the
driving losses in a SR system, it is necessary to determine the
gate charge of the MOSFET for operation specifically in a
ZVS system. Some manufacturers define this parameter as
Q
data. If the C
it will need to be measured. Please note that the input
capacitance is not linear (as shown Figure 53) and it needs
to be characterized for a given gate voltage clamp level.
Step 2 – Gate drive losses calculation:
voltage. Gate driver clamp voltage selection depends on the
type of MOSFET used (threshold voltage versus channel
resistance). The total power losses (driving loses and
conduction losses) should be considered when selecting the
gate driver clamp voltage. Most of today’s MOSFETs for SR
systems feature low R
g_total
g_ZVS
Note that R
It is important to consider the power dissipation in the
In SR systems the body diode of the SR MOSFET starts
Therefore, the input capacitance of a MOSFET operating
Gate drive losses are affected by the gate driver clamp
, of most MOSFETs on the market is defined for hard
. Unfortunately, most datasheets do not provide this
iss
drain1
(or Q
Figure 53. Typical MOSFET Capacitances Dependency on V
and R
g_ZVS
DS(on)
drain2
) parameter is not available then
for 5 V V
should be designed in such
gs
voltage and thus it
th_cs_on
iss
capacitance
off
threshold
and T
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on
23
off process always starts before the drain to source voltage
rises up significantly. Therefore, the MOSFET switch
always operates under Zero Voltage Switching (ZVS)
conditions
rectification system.
the power dissipation and DIE temperature of the
NCP4303A/B controller. Note that real results can vary due
to the effects of the PCB layout on the thermal resistance.
Step 1 – MOSFET gate to source capacitance:
not have a Miller effect like in hard switching systems
because the drain to source voltage is close to zero and its
change is negligible.
is beneficial to use NCP4303B. However, there is still a big
group of MOSFETs on the market that require higher gate
to source voltage − in this case the NCP4303A should be
used.
gate driver clamp voltage and the input capacitance of the
MOSFET:
Where:
V
V
C
ZVS mode
f
the IC, but also in external resistances like the external gate
resistor (if used) and the MOSFET internal gate resistance
(Figure 54). Because NCP4303A/B features a clamped
driver, it’s high side portion can be modeled as a regular
driver switch with equivalent resistance and a series voltage
source. The low side driver switch resistance does not drop
sw
P
g_ZVS
cc
clamp
The following steps show how to approximately calculate
During ZVS operation the gate to drain capacitance does
The total driving loss can be calculated using the selected
The total driving power loss won’t only be dissipated in
DRV_total
is the switching frequency of the target application
is the NCP4303x supply voltage
is the driver clamp voltage
is the gate to source capacitance of the MOSFET in
+ V
when
CC
ds
@ V
C
and V
C
C
implemented
oss
iss
clamp
rss
+ C
+ C
+ C
gs
@ C
Voltages
gs
ds
gd
g_ZVS
) C
) C
gd
gd
@ f
in
SW
a
synchronous
(eq. 8)