MCIMX6Q6AVT10AC Freescale Semiconductor, MCIMX6Q6AVT10AC Datasheet
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... Each processor provides a 64-bit DDR3/LVDDR3/LPDDR2-1066 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, hard drive, displays, and camera sensors. © 2012-2013 Freescale Semiconductor, Inc. All rights reserved. Document Number: IMX6DQAxEC Rev. 2, 04/2013 MCIMX6QxAxxxxC MCIMX6DxAxxxxC Package Information Case FCPBGA mm, 0 ...
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... Integrated power management—The processors integrate linear regulators and internally generate voltage levels for different domains. This significantly simplifies system power management structure. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev ® ES 2.0 3D graphics accelerator with four shaders (up to 200 MT serial audio, SATA-II, and PCIe-II). Freescale Semiconductor ...
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... The latest part numbers are available on freescale.com/imx6series. If your desired part number is not listed in freescale.com/imx6series or contact your Freescale representative. Table 1. Example Automotive Grade Orderable Part Numbers Part Number Quad/Dual CPU MCIMX6Q6AVT10AC i.MX 6Quad MCIMX6Q4AVT10AC i.MX 6Quad MCIMX6Q6AVT08AC i.MX 6Quad MCIMX6Q4AVT08AC i ...
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... Fusing % Real Codec off and no HDCP or DTCP A Real Codec off with HDCP on C Frequency $$ 800 MHz (Industrial grade 850 MHz (Automotive grade GHz 3 10 1.2 GHz 12 Package type RoHS FCPBGA 21x21 0.8mm (lidded) VT FCPBGA 21x21 0.8mm (non lidded) YM Freescale Semiconductor ...
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... SD and SDIO cards up to UHS-I SDR-104 mode (104 MB/s max) – 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards MHz in both SDR and DDR modes (104 MB/s max) i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Introduction 5 ...
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... The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE). i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev Mbps Freescale Semiconductor ...
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... Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal name changes is in the document, IMX 6 Series Signal Name Mapping (EB792). This list can be used to map the signal names used in older documentation to the new standardized naming conventions. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Introduction 7 ...
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... CCM GPC SRC XTALOSC OSC32K MMC/SD AP Peripherals eMMC/eSD uSDHC (3) uSDHC MMC/SD AUDMUX SDXC I2C (3) PWM (4) OCOTP Modem IC IOMUXC KPP GPIO Keypad CAN (2) 1-Gbps ENET MLB 150 Ethernet DTCP 10/100/1000 HSI/MIPI Mbps USB OTG + 2xHSIC 3 HS Ports PHY MLB/Most Network Freescale Semiconductor ...
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... SRC Power Controller, System Reset Controller i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 2. i.MX 6Dual/6Quad Modules List Subsystem Electrical Fuse Array. Enables to setup Boot Modes, Security Levels, Security Keys, and many other system parameters. The i.MX 6Dual/6Quad processors consist of 512x8-bit fuse box ...
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... Note: The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE). Brief Description Freescale Semiconductor ...
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... General Purpose Media Interface GPT General Purpose Timer i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Subsystem Timer Each EPIT is a 32-bit “set and forget” timer that starts counting after the Peripherals EPIT is enabled by software capable of providing precise interrupts at regular intervals with minimal processor intervention ...
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... Support for display backlight reduction Connectivity KPP Supports external key pad matrix. KPP features are: Peripherals • Open drain design • Glitch suppression circuit design • Multiple keys detection • Standby key press detection Brief Description Freescale Semiconductor ...
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... KB RAM RAM Internal RAM 256 KB i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Subsystem LVDS Display Bridge is used to connect the IPU (Image Processing Unit) Peripherals to External LVDS Display Interface. LDB supports two channels; each channel has following signals: • One clock pair • ...
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... Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, Master Key Control, and Violation/Tamper Detection and reporting. Multimedia A standard audio file transfer format, developed jointly by the Sony and Peripherals Phillips corporations. It supports Transmitter and Receiver functionality. Brief Description Freescale Semiconductor ...
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... UART-5 USBOH3A USB 2.0 High Speed OTG and 3x HS Hosts i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Subsystem Connectivity The SSI is a full-duplex synchronous interface, which is used on the Peripherals processor to provide connectivity with off-chip audio peripherals. The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths ( bits per word), and clock / frame sync options ...
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... VPU’s decoding/encoding capabilities. Timer The Watchdog Timer supports two comparison points during each Peripherals counting period. Each of the comparison points is configurable to evoke an interrupt to the ARM core, and a second point evokes an external event on the WDOG line. Brief Description Freescale Semiconductor ...
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... The recommended connections for unused analog interfaces can be found in the section, “Unused analog interfaces,” of the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG). i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Subsystem Timer The TrustZone Watchdog (TZ WDOG) timer module protects against ...
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... CAUTION Table 4 may affect reliability or cause Table 4. Absolute Maximum Ratings Symbol VDD_ARM_IN VDD_ARM23_IN VDD_SOC_IN VDD_ARM_CAP VDD_ARM23_CAP VDD_SOC_CAP VDD_PU_CAP Supplies denoted as I/O supply Supplies denoted as I/O supply Table 3 for a quick Topic appears … Min Max Unit -0.3 1.5 V -0.3 1.3 V -0.5 3.6 V -0.4 1.975 V Freescale Semiconductor ...
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... Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Symbol Supplies denoted as I/O supply Supplies denoted as I/O supply ...
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... VDD_HIGH_IN, if the system does not require keeping real time and other data on OFF state. — — LPDDR2 DDR3 DDR3_L • 1.15 V – 1. HSIC 1.2 V mode • 1.43 V – 1. RGMII 1.5 V mode • 1.70 V – 1. RGMII 1.8 V mode • 2.25 V – 2.625 V in RGMII 2.5 V mode Freescale Semiconductor ...
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... I/O pins need to have a pull-up or pull-down resistor applied to limit any floating gate current. 9 This supply also powers the pre-drivers of the DDR I/O pins; therefore, it must always be provided, even when LVDS is not used. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 6. Operating Ranges (continued) 1 Min ...
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... On-Chip Loads Load NVCC_LVDS_2P5 Board-level connection to VDD_HIGH_CAP NVCC_MIPI HDMI_VPH PCIE_VPH SATA_VPH 3 VDD_CACHE_CAP Board-level connection to VDD_SOC_CAP HDMI_VP PCIE_VP PCIE_VPTX SATA_VP Table 8. External Input Clock Frequency Symbol Min f — ckil f — xtal Comment Typ Max 3 32.768 /32.0 — 24 — Freescale Semiconductor Unit kHz MHz ...
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... VDD_ARM_IN VDD_SOC_IN VDD_HIGH_IN VDD_SNVS_IN USB_OTG_VBUS/USB_H1_VBUS (LDO 3P0) i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor are required for use with Freescale BSPs to ensure precise time Table 9 represent a use case designed specifically to show the Table 9. Maximum Supply Currents Conditions 996 MHz ARM clock based on Power ...
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... Use maximum IO equation 5 Use maximum IO equation 5 Use maximum IO equation 5 Use maximum IO equation 5 Use maximum IO equation 5 Use maximum IO equation 5 Use maximum IO equation 5 Use maximum IO equation 5 Use maximum IO equation 5 Use maximum IO equation 5 Use maximum IO equation 5 Use maximum IO equation 25 Table 9. The maximum VDD_SNVS_IN Freescale Semiconductor ...
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... SRTC running 1 The typical values shown here are for information only and are not guaranteed. These values are average values measured on a worst-case wafer at 25C. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Test Conditions Electrical Characteristics 1 Supply Typical VDD_ARM_IN (1 ...
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... Table 12. SATA PHY Current Drain Test Conditions Supply Single Transceiver SATA_VP SATA_VPH Clock Module SATA_VP SATA_VPH Single Transceiver SATA_VP SATA_VPH Clock Module SATA_VP SATA_VPH Single Transceiver SATA_VP SATA_VPH Clock Module SATA_VP SATA_VPH NVCC_PLL_OUT (1.1 V) <0.5 A Typical Current Unit 6.9 6 6.9 6.2 9.4 mA 2.9 6.9 6.2 Freescale Semiconductor ...
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... LOS and POR enabled 3 PDDQ mode 1 Programmed for 1.0 V peak-to-peak Tx level. 2 Programmed for 0.9 V peak-to-peak Tx level with no boost or attenuation. 3 LOW power non-functional. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Test Conditions Supply Single Transceiver SATA_VP SATA_VPH Clock Module SATA_VP SATA_VPH Single Transceiver ...
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... Test Conditions Supply 5G Operations PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) 2.5G Operations PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2 Operations PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) 2.5G Operations PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) — PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) — PCIE_VP (1.1 V) PCIE_VPTX (1.1 V) PCIE_VPH (2.5 V) Max Current Unit 2 2 2.4 12 1.3 mA 0.18 0.36 Freescale Semiconductor ...
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... Bit rate 251.75 Mbps Bit rate 279.27 Mbps Bit rate 742.5 Mbps Bit rate 1.485 Gbps Bit rate 2.275 Gbps Bit rate 2.97 Gbps Power-down i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 14. HDMI PHY Current Drain Supply HDMI_VPH HDMI_VP HDMI_VPH HDMI_VP HDMI_VPH ...
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... V supply (for example, from the external components that use both the 1.8 V and 3.3 V supplies). USB_OTG_VBUS and USB_H1_VBUS are not part of the power supply sequence and can be powered at any time. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev NOTE NOTE NOTE Freescale Semiconductor ...
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... Power Gate. The regulation FET is switched fully off limiting the current draw from the supply. The analog part of the regulator is powered down here limiting the power consumption. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor 147. NOTE Electrical Characteristics Table 101, " ...
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... For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG). For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM). i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev Freescale Semiconductor ...
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... MHz PLL Table 16. 528 MHz PLL Electrical Parameters Parameter Clock output range Reference clock Lock time i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Electrical Characteristics Value 650 MHz ~1.3 GHz 24 MHz <11250 reference cycles Value 528 MHz PLL output 24 MHz < ...
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... Automotive and Infotainment Applications Processors, Rev Table 19. MLB PLL Electrical Parameters Table 20. ARM PLL Electrical Parameters Value 500 MHz 24 MHz <11250 reference cycles Value 480 MHz PLL output 24 MHz <383 reference cycles Value <1.5 ms Value 650 MHz~1.3 GHz 24 MHz <2250 reference cycles Freescale Semiconductor ...
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... Fosc — 32.768 kHz 4 A Current — consumption i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor NOTE Table 21. OSC32K Main Characteristics Max — This frequency is nominal and determined mainly by the crystal selected. 32.0 K would work as well. — The typical value shown is only for the oscillator, driven by an external crystal. If the internal ring oscillator is used instead of an external crystal, then approximately 25 ...
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... PCB on either side of the quartz. A higher Cload will decrease oscillation margin, but increases current oscillating through the crystal. will decrease the oscillating margin. NOTE ovdd pmos (Rpu) pdat pad Predriver nmos (Rpd) ovss Comments Voh min Vol max Freescale Semiconductor ...
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... Input current (22 k pull-up) Input current (47 k pull-up) Input current (100 k pull-up) Input current (100 k pull-down) Keeper circuit resistance Rkeep i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Symbol Test Conditions Vih — Vil — Vih — ...
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... Min Max Unit 0.9 OVDD — 0.1 OVDD — 0.49 OVDD 0.51 OVDD Vref+0.13V OVDD OVSS Vref-0.13V 2 0.26 See Note 2 See Note -0.26 -2.5 2.5 -15 +15 — 10 110 175 Table 6, unless otherwise Freescale Semiconductor — — A % k ...
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... Symbol Output Differential Voltage V Output High Voltage V Output Low Voltage V Offset Voltage V i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Symbol Test Conditions Ioh = -0.1 mA Voh (DSE = 001) Voh Ioh = -1 mA Voh (for all except DSE = 001) Iol = 0.1 mA Vol (DSE = 001) ...
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... O From Output Test Point Under Test CL CL includes package, probe and fixture capacitance Figure 4. Load Circuit for Output 80% 20% tr Figure 5. Output Transition Time Waveform Min Max Unit 300 500 mV 1.15 1.75 V 0.75 1. 1.5 V 1.6 — k Figure 4 and OVDD 80% 20 Freescale Semiconductor ...
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... Drive. ipp_dse=001) 1 Input Transition Times 1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Symbol Test Condition tr Cload, slow slew rate 15 pF Cload, fast slew rate tr, tf ...
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... Min Typ Max Vref + 0.175 — OVDD 0 — Vref – 0.175 0.35 — — Vref – 0.15 — Vref + 0.15 — — 0.4 — — 0.5 Freescale Semiconductor Unit V-ns V/ns ns Unit V-ns ...
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... Measurement levels are 20–80% from output voltage. 4.7.4 MLB 6-Pin I/O AC Parameters The differential output transition time waveform is shown in i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Symbol Test Condition tsr Driver impedance = 34 t clk = 533 MHz ...
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... Symbol Test Condition t SKD Rload = 50 t between padP TLH t THL fclk_ext fclk_pll 20% t THL Min Typ Max — — 0.1 — — 1 and padN — — 1 — — — 102.4 — — — 307.2 Freescale Semiconductor Unit ns MHz MHz ...
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... Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor NOTE Figure 9). Electrical Characteristics ...
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... Vref2 Rpd = Vovdd – Vref2 Figure 9. Impedance Matching Load for Measurement i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev OVDD PMOS (Rpu) Ztl inches pad NMOS (Rpd) OVSS Vin (do) Vref2 Ztl Ztl Cload = 1p t,(ns) Vout (pad) t,(ns) Freescale Semiconductor ...
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... Table 35 shows the GPIO output buffer impedance (OVDD 3.3 V). Table 35. GPIO Output Buffer Average Impedance (OVDD 3.3 V) Parameter Symbol Output Driver Rdrv Impedance i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Drive Strength (ipp_dse) Typ Value 001 010 011 100 101 110 ...
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... NVCC_DRAM=1.5 V (DDR3) DDR_SEL=11 Drive Strength (DSE) = 000 001 010 011 100 101 110 111 Test Conditions Z — O Typical Unit NVCC_DRAM=1.2 V (LPDDR2) DDR_SEL=10 Hi-Z Hi-Z 240 240 120 120 Min Typ Max 1.6 — — Freescale Semiconductor Unit k ...
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... WDOG1_B output signals (for each one of the Watchdog modules) do not have dedicated pins, but are muxed out through the IOMUX. See the IOMUX manual for detailed information. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 38 lists the timing parameters. CC1 Figure 10 ...
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... Bit 16 Bit MUM = 0, MUM = 0, MUM = 1, DSZ = 010 DSZ = 011 DSZ = 001 EIM_AD EIM_AD EIM_AD [15:00] [15:00] [15:00] EIM_ADDR EIM_ADDR EIM_ADDR [25:16] [25:16] [25:16] — EIM_DATA EIM_AD [07:00] [07:00] — EIM_DATA EIM_AD [15:08] [15:08] EIM_DATA EIM_DATA — [23:16] [23:16] EIM_DATA EIM_DATA — [31:24] [31:24] Freescale Semiconductor 32 Bit MUM = 1, DSZ = 011 EIM_AD [15:00] EIM_DATA [09:00] EIM_AD [07:00] EIM_AD [15:08] EIM_DATA [07:00] EIM_DATA [15:08] ...
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... Parameter WE1 EIM_BCLK cycle time WE2 EIM_BCLK high level width WE3 EIM_BCLK low level width i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor specify the timings related to the EIM module. All EIM output control WE2 ... WE1 WE4 WE6 WE8 WE10 ...
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... Unit ns — — — — — — — ns — ns — ns — ns — ns Freescale Semiconductor ...
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... Figure 14. Synchronous Memory Read Access, WSC=1 EIM_BCLK Last Valid Address EIM_ADDRxx EIM_CSx_B EIM_WE_B EIM_LBA_B EIM_OE_B EIM_EBx_B EIM_DATAxx Figure 15. Synchronous Memory, Write Access, WSC=1, WBEA=0 and WADVN=0 i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor WE5 WE4 Address v1 WE6 WE6 WE7 WE14 WE15 WE10 WE11 WE12 ...
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... WE16 WE5 WE4 Address V1 Address WE6 WE8 WE14 WE15 WE10 WSC=6,ADVA=0, ADVN=1, and ADH=1 NOTE WE4 WE5 Address V1 Address WE6 WE15 WE10 WSC=7, RADVN=1, ADH=1, OEA=0 WE17 Write Data WE7 WE9 WE11 WE19 Data WE18 WE7 WE11 WE13 Freescale Semiconductor ...
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... EIM_ADDRxx/ Last Valid Address EIM_ADxx EIM_WE_B EIM_LBA_B EIM_OE_B EIM_EBx_B EIM_DATA[07:00] Figure 18. Asynchronous Memory Read Access (RWSC = 5) i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 42 provide timing parameters relative to the chip select (CS) state start of access MAXCSO WE31 Address V1 WE39 WE35 ...
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... Figure 20. Asynchronous Memory Write Access i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev start of access MAXCSO MAXDI WE31 Addr. V1 WE32A WE40A WE39 WE35A WE37 MAXCO WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 end of access D(V1) WE44 WE36 WE38 WE32 Next Address WE34 WE40 WE46 WE42 Freescale Semiconductor ...
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... Figure 21. Asynchronous A/D Muxed Write Access EIM_CSx_B EIM_ADDRxx Last Valid Address EIM_WE_B EIM_LBA_B EIM_OE_B EIM_EBx_B EIM_DATAxx[07:00] EIM_DTACK_B Figure 22. DTACK Mode Read Access (DAP=0) i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor WE41A WE31 D(V1) Addr. V1 WE32A WE33 WE40A WE39 WE45 WE31 Address V1 ...
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... CSN -3 + (ADVN + — ADVA + 1 - CSA) — (WEA - WCSA) — (WEN_WCSN) — (OEA - RCSA (OEA + 3 + (OEA + RADVN+RADVA RADVN+RADVA+AD +ADH+1-RCSA) H+1-RCSA) — (OEN - RCSN) — (RBEA - RCSA) — (RBEN - RCSN) — (ADVA - CSA) Freescale Semiconductor Unit ...
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... WE48 EIM_CSx_B Invalid to EIM_DTACK_B invalid 1 For more information on configuration parameters mentioned in this table, see the i.MX 6Solo/6DualLite reference manual (IMX6DQRM). i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Determination by Synchronous measured parameters WE7 - WE15 - CSN WE14 - WE6 + (ADVN + ADVA + -3 + (ADVN + 1 - CSA) ...
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... DDR1 DRAM_SDCLKx_P clock high-level width DDR2 DRAM_SDCLKx_P clock low-level width i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev DDR4 DDR5 DDR5 DDR4 DDR5 DDR5 DDR4 DDR7 COL/BA Symbol DDR1 DDR2 CK = 532 MHz Unit Min Max 0.47 0. 0.47 0. Freescale Semiconductor ...
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... DRAM_DQMx (output) DDR17 ID DDR17 DRAM_DATAxx and DRAM_DQMx setup time to DRAM_SDQSx_P (differential strobe) DDR18 DRAM_DATAxx and DRAM_DQMx hold time to DRAM_SDQSx_P (differential strobe) DDR21 DRAM_SDQSx_P latching rising transitions to associated clock edges i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Symbol ...
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... Automotive and Infotainment Applications Processors, Rev Parameter DATA DATA DATA DATA DDR26 Figure 26. DDR3/DDR3L Read Cycle Table 45. DDR3/DDR3L Read Cycle Parameter Symbol CK = 532 MHz Symbol Min Max t 0.45 0.55 DQSH t 0.45 0.55 DQSL DATA DATA DATA DATA CK = 532 MHz Unit Min Max — 450 — ps Freescale Semiconductor Unit tCK tCK ...
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... LP4 DRAM_ADDRxx hold time 1 All measurements are in reference to Vref level. Measurements were done using balanced load and 25 resistor from outputs to DRAM_VREF. 2 i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor LP4 LP3 LP4 LP4 LP3 Table 46. LPDDR2 Timing Parameter Symbol ...
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... Figure 28. LPDDR2 Write Cycle Table 47. LPDDR2 Write Cycle Parameter LP23 LP18 Data Data Data Data LP18 CK = 532 MHz Symbol Min Max t 235 — 235 — -0.25 +0.25 DQSS t 0.4 — DQSH t 0.4 — DQSL Freescale Semiconductor Unit ps ps tCK tCK tCK ...
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... The i.MX 6Dual/6Quad GPMI controller is a flexible interface NAND Flash controller with 8-bit data width 200 MB/s I/O speed and individual chip select. It supports Asynchronous timing mode, Source Synchronous timing mode, and Samsung Toggle timing mode separately described in the following subsections. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor DATA DATA DATA DATA LP26 Figure 29 ...
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... Figure 30. Command Latch Cycle Timing Diagram Figure 31. Address Latch Cycle Timing Diagram Figure 32. Write Data Latch Cycle Timing Diagram i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev describes the timing parameters (NF1–NF17) that are shown in the figures. Figure 30 through Figure 33 Freescale Semiconductor ...
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... NF12 Ready to NAND_RE_B low NF13 NAND_RE_B pulse width NF14 READ cycle time NF15 NAND_RE_B high hold time i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor T = GPMI Clock Cycle Symbol Min (AS + DS) 0.12 [see tCLS DH 0.72 [see tCLH ( T [see tCS (DH+1) ...
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... MT/s EDO mode. However, if the board delay is large enough and cannot be ignored, the delay value should be made larger to compensate the board delay. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev GPMI Clock Cycle Symbol Min tDSR — 5,6 tDHR 0.82/11.83 [see ] 1 (continued) Timing Max (DS T -0.67)/18.38 [see 5,6 ] — (Figure Freescale Semiconductor Unit ns ns 33). ...
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... Source Synchronous Mode AC Timing (ONFI 2.x Compatible) Figure 35 shows the write and read timing of Source Synchronous mode. Figure 35. Source Synchronous Mode Command and Address Timing Diagram i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Electrical Characteristics 69 ...
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... Electrical Characteristics Figure 36. Source Synchronous Mode Data Write Timing Diagram Figure 37. Source Synchronous Mode Data Read Timing Diagram i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev Freescale Semiconductor ...
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... Generally, the typical delay value of this register is equal to 0x7 which means 1/4 clock cycle delay expected. However, if the board delay is large enough and cannot be ignored, the delay value should be made larger to compensate the board delay. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Electrical Characteristics 1 Timing ...
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... Samsung Toggle mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing. See Section 4.10.1, “Asynchronous Mode AC Timing (ONFI 1.0 Compatible)” 4.10.3.2 Read and Write Timing Figure 39. Samsung Toggle Mode Data Write Timing i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev for details. Freescale Semiconductor ...
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... Command/address NAND_DATAxx setup time NF9 Command/address NAND_DATAxx hold time NF18 NAND_CEx_B access time NF22 clock period NF23 preamble delay NF24 postamble delay i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor 1 Timing T = GPMI Clock Cycle Symbol Min (AS + DS) 0.12 [see tCLS DH ...
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... This section describes the timing parameters of the ECSPI block. The ECSPI has separate timing parameters for master and slave modes. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev (continued) Timing T = GPMI Clock Cycle Symbol Min 0.25 tCK - 0.32 6 tDS 6 0.25 tCK - 0.79 tDH 7 tDQSQ — 7 tQHS — Unit Max — ns — ns 3.18 — 3.27 — Freescale Semiconductor ...
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... ECSPI3/DISP0_DAT2 2 ECSPI fast includes: ECSPI1/EIM_D17, ECSPI4/EIM_D22, ECSPI5/SD2_DAT0, ECSPI5/SD1_DAT0 3 See specific I/O AC parameters Section 4.7, “I/O AC Parameters.” 4 ECSPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 52 CS2 CS3 CS2 CS3 Symbol t clk t ...
Page 76
... CS6 CS2 CS2 Symbol t clk Half ECSPIx_SCLK period CSLH t SCS t HCS t Smosi t Hmosi = 20 pF) t LOAD PDmiso CS5 CS4 Min Max Unit — — — — — — — Freescale Semiconductor ...
Page 77
... ESAI_RX_FS input hold time after ESAI_RX_CLK falling edge 78 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) high 79 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) low 80 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) 5 high i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Figure 44. 1,2 Symbol t SSICC — — — — ...
Page 78
... T 15 — — C — — 18.0 — — — 18.0 — Freescale Semiconductor 3 Unit ...
Page 79
... ESAI_TX_CLK (Input/Output) ESAI_TX_FS (Bit) Out ESAI_TX_FS (Word) Out Data Out ESAI_TX_FS (Bit) In ESAI_TX_FS (Word) In i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor First Bit Figure 43. ESAI Transmitter Timing Electrical Characteristics 83 87 Last Bit 91 79 ...
Page 80
... Electrical Characteristics ESAI_RX_CLK (Input/Output) ESAI_RX_FS (Bit) Out ESAI_RX_FS (Word) Out Data In ESAI_RX_FS (Bit) In ESAI_RX_FS (Word) In i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev First Bit Figure 44. ESAI Receiver Timing 70 72 Last Bit 75 Freescale Semiconductor ...
Page 81
... Clock High Time SD4 Clock Rise Time SD5 Clock Fall Time eSDHC Output/Card Inputs SD_CMD, SD_DATAx (Reference to SDx_CLK) SD6 eSDHC Output Delay i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 55 lists the SD/eMMC4.3 timing characteristics. SD4 SD2 SD1 SD5 SD3 SD6 ...
Page 82
... SD4 Figure 46. eMMC4.4/4.41 Timing Symbols Card Input Clock ISU t IH Min Max 2.5 — ISU t 1.5 — IH – 25 MHz. In high-speed mode, – 20 MHz. In high-speed mode, clock SD1 ...... ...... Min Max Unit 0 52 MHz 0 50 MHz 2.5 7.1 ns 2.6 — ns 1.5 — ns Freescale Semiconductor Unit ns ns ...
Page 83
... SD7 uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK) Card Output Data Window SD8 1 Data window in SDR100 mode is variable. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 55 lists the SDR50/SDR104 timing Figure 47. SDR50/SDR104 Timing Symbols Card Input Clock t CLK 0.3 ...
Page 84
... ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev Table 58 describes the timing parameters (M1–M4) shown Table 58. MII Receive Signal Timing 1 37. M4 Min Max Unit 5 — — ns 35% 65% ENET_RX_CLK period 35% 65% ENET_RX_CLK period Freescale Semiconductor ...
Page 85
... ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode. 4.11.5.1.3 MII Asynchronous Inputs Signal Timing (ENET_CRS and ENET_COL) Figure 50 shows MII asynchronous input timings. the figure. ENET_CRS, ENET_COL i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 59 describes the timing parameters (M5–M8) shown Table 59. MII Transmit Signal Timing 1 ...
Page 86
... Automotive and Infotainment Applications Processors, Rev Min 1.5 Table 61 describes the timing parameters (M10–M15) M14 M15 M10 M11 M12 M13 Min 0 — 40% 40% Max Unit — ENET_TX_CLK period Max Unit — — ns — ns 60% ENET_MDC period 60% ENET_MDC period Freescale Semiconductor ...
Page 87
... M19 ENET_CLK to ENET0_TXD[1:0], ENET_TX_EN valid M20 ENET_RXD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to ENET_CLK setup M21 ENET_CLK to ENET_RXD[1:0], ENET_RX_EN, ENET_RX_ER hold i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 62 describes the timing parameters (M16–M21) shown in the M16 M18 M19 M20 M21 Table 62. RMII Signal Timing ...
Page 88
... Tcyc of the lowest speed transitioned between. Figure 53. RGMII Transmit Signal Timing Diagram Original i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev Description 1 Min Max Unit 7.2 8.8 ns -100 900 — 0.75 ns Freescale Semiconductor ...
Page 89
... HDMI Module Timing Parameters 4.11.7.1 Latencies and Timing Information Power-up time (time between TX_PWRON assertion and TX_READY assertion) for the HDMI 3D Tx PHY while operating with the slowest input reference clock supported (13.5 MHz) is 3.35 ms. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Electrical Characteristics 89 ...
Page 90
... Symbol Parameter avddtmds Termination supply voltage i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev Figure 56. Driver Measuring Conditions Figure 57. Driver Definitions Figure 58. Source Termination Table 64. Electrical Characteristics Condition Operating conditions for HDMI — Min Typ Max Unit 3.15 3.3 3.45 V Freescale Semiconductor ...
Page 91
... HDMI 3D Tx PHY. various parameters specified in table. All dynamic parameters related to the TMDS line drivers’ performance imply the use of assembly guidelines. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Condition — TMDS drivers DC specifications ...
Page 92
... Electrical Characteristics Figure 60. Eye Diagram Mask Definition for HDMI Driver Signal Specification at TP1 i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev TMDSCLK 50 CPL CPH Figure 59. TMDS Clock Signal Definitions Figure 61. Intra-Pair Skew Definition Freescale Semiconductor ...
Page 93
... TMDSCLK jitter t Intra-pair (pulse) skew SK(p) t Inter-pair skew SK(pp) t Differential output signal rise R time i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Figure 62. Inter-Pair Skew Definition Table 65. Switching Characteristics Conditions TMDS Drivers Specifications — On TMDSCLKP/N outputs See Figure 59 ...
Page 94
... Standard Mode Fast Mode Min Max Min 10 — 2.5 4.0 — 0.6 4.0 — 0 3.45 0 4.0 — 0.6 4.7 — 1.3 4.7 — 0.6 3 250 — 100 Freescale Semiconductor Unit START Unit Max µ — s µ — s µ — µ 0.9 s µ — s µ — s µ — s — ...
Page 95
... Related image processing and manipulation: sensor image signal processing, display processing, image conversions, and other related functions. • Synchronization and control capabilities, such as avoidance of tearing artifacts. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor 2 C Module Timing Parameters (continued) Standard Mode Min 4.7 — ...
Page 96
... R/G/B[4] R/G/B[0] Y/C[0] R/G/B[5] R/G/B[1] Y/C[1] R/G/B[0] R/G/B[2] Y/C[2] R/G/B[1] R/G/B[3] Y/C[3] R/G/B[2] R/G/B[4] Y/C[4] R/G/B[3] R/G/B[5] Y/C[5] R/G/B[4] R/G/B[6] Y/C[6] R/G/B[5] R/G/B[7] Y/C[ RGB565 YCbCr YCbCr 16 bits 16 bits 16 bits 2 cycles 1 cycle 1 cycle — — 0 — — 0 — — C[0] — — C[1] B[0] C[0] C[2] B[1] C[1] C[3] B[2] C[2] C[4] B[3] C[3] C[5] B[4] C[4] C[6] G[0] C[5] C[7] G[1] C[6] 0 G[2] C[7] 0 G[3] Y[0] Y[0] G[4] Y[1] Y[1] G[5] Y[2] Y[2] R[0] Y[3] Y[3] R[1] Y[4] Y[4] R[2] Y[5] Y[5] R[3] Y[6] Y[6] R[4] Y[7] Y[7] Freescale Semiconductor 8 YCbCr 20 bits 1 cycle C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] C[8] C[9] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Y[8] Y[9] ...
Page 97
... IPU2_CSIx_DATA_EN bus. 4.11.10.2.2 Gated Clock Mode The IPU2_CSIx_VSYNC, IPU2_CSIx_HSYNC, and IPU2_CSIx_PIX_CLK signals are used in this mode. See Figure 65. Figure 65. Gated Clock Mode Timing Diagram i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Electrical Characteristics 97 ...
Page 98
... IPU2_CSIx_PIX_CLK. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev Section 4.11.10.2.2, “Gated Clock nth frame invalid 1st byte is that of a typical sensor. Some other sensors may have a slightly Mode,”) Figure 66). All incoming pixel clocks n+1th frame invalid 1st byte Freescale Semiconductor ...
Page 99
... IPUx_DISPx_DAT02 DAT[2] IPUx_DISPx_DAT03 DAT[3] IPUx_DISPx_DAT04 DAT[4] IPUx_DISPx_DAT05 DAT[5] IPUx_DISPx_DAT06 DAT[6] i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor lists the sensor interface timing characteristics. IP2 IP3 Figure 67. Sensor Interface Timing Diagram Symbol Fpck Tsu Thd Table 69 Table 69. Video Signal Cross-Reference ...
Page 100
... Y[3] — Y[4] — Y[5] — — Y[6] — — Y[7] — — Y[8] — — Y[9] — — — — — — — — — — — — — — May be required for anti-tearing — VSYNC out Additional frame/row synchronous signals with programmable timing Freescale Semiconductor ...
Page 101
... There are special physical outputs to provide synchronous controls: • The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display (component, pixel) clock for a display. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor LCD RGB/TV Signal Allocation (Example) 16-bit 18-bit ...
Page 102
... LCD interface timing for a generic active matrix color TFT panel. In this figure, signals are shown with negative polarity. The sequence of events for active matrix interface timing is: • DI_CLK internal DI clock is used for calculation of other controls. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 102 NOTE Freescale Semiconductor ...
Page 103
... All the parameters shown in the figure are programmable. All controls are started by corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor LINE 2 LINE 3 LINE 4 ...
Page 104
... All parameters shown in the figure are programmable. IP13 VSYNC HSYNC DRDY Figure 70. TFT Panels Timing Diagram—Vertical Sync Pulse i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 104 IP8o IP8 IP9o IP9 Start of frame IP14 IP12 IP7 IP5 IP10 IP6 End of frame IP15 Freescale Semiconductor ...
Page 105
... IP9 Horizontal blank interval 1 IP10 Horizontal blank interval 2 IP12 Screen height IP13 VSYNC width IP14 Vertical blank interval 1 IP15 Vertical blank interval 2 i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Figure 69 Symbol Value 1 Tdicp (see ) Tdpcp DISP_CLK_PER_PIXEL Tdicp Tsw (SCREEN_WIDTH) ...
Page 106
... DRDY_OFFSET—offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the bus, in DI_CLK 2 (0.5 DI_CLK Resolution). The DRDY_OFFSET should be built by suitable DI’s counter. for integer DISP_CLK_PERIOD --------------------------------------------------- - DI_CLK_PERIOD for fractional DISP_CLK_PERIOD --------------------------------------------------- - DI_CLK_PERIOD Freescale Semiconductor Unit ...
Page 107
... The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 2 Display interface clock down time i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Accuracy = T diclk 0.62ns ...
Page 108
... Transient voltage range is limited from -300 mV to 1600 mV VGNDSH(min VGNDSH(max) + VOH(absmax) Lane module in LP Receive Mode — Min Max Units 250 450 mV 1.25 1.6 mV 0.9 1.25 mV 1.15 1.375 247 454 mV Min Typ Max Unit -50 — 1350 mV -10 — -50 — Freescale Semiconductor ...
Page 109
... Differential input low voltage IDTL threshold V Single ended input high IHHS voltage i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Test Conditions — — HS Line Drivers DC Specifications 80 = RL< = 125 80 = RL< = 125 80 = RL< = 125 80 = RL< = 125 ...
Page 110
... Figure 72 shows both V OH,MAX OH,MIN GNDSH, GND V GNDSH,MIN LP Single-ended Signaling Freescale Semiconductor Unit mV mV ...
Page 111
... Figure 74. Possible 4.11.12.5 D-PHY Switching Characteristics Symbol Parameters — Maximum serial data rate (forward direction) F DDR CLK frequency DDRCLK P DDR CLK period DDRCLK i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor OD(0) OD(0) VOD Distortions of the Single-ended HS Signals ...
Page 112
... L 0 — 70 — — 200 -50 — 50 — — 60 — — 300 50 — — — — 400 450 — — — — 1 — — 2 Freescale Semiconductor Unit % pk- rms mV/ns pF mVpp mVpp pF Vps ns mV MHz pF pF ...
Page 113
... Figure 76: 4.11.12.8 Reverse High-Speed Data Transmission Timing NRZ Data CLKn CLKp Figure 77. Reverse High-Speed Data Transmission Timing at Slave Side i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Test Conditions — — — 1 Data Bit Time = 1UI 1 Data Bit Time = 1UI UI (1) ...
Page 114
... LPX e SPIKE T MIN-RX Last bit of frame N-bits Frame Last bit of Last bit of frame frame E. D. Ready shall F. Ready G. Ready Ready maintain zero of if shall can change can receiver does not maintain change have free space its value Freescale Semiconductor ...
Page 115
... Channel Description bits DATA FLAG Complete N-bits Frame READY Figure 83. Stream Transmission Mode Frame Transfer (Synchronized Data Flow) i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Last bit of First bit of frame frame Receiver has captured a complete Frame C PHY Frame 3. First bit received 4 ...
Page 116
... Automotive and Infotainment Applications Processors, Rev. 2 116 Complete N-bits Frame Complete N-bits Frame Table 75. DATA and FLAG Timing Description 1 Mbit/s 100 Mbit/s 1000 0.5 ns 400 350 ns 3.5 ns Freescale Semiconductor ...
Page 117
... Parameter Differential output voltage (steady-state Difference in differential output voltage between (high/low) steady-states OD, high OD, low i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor 50% t Rise 80% 80% 50% 20% 20% t Fall t TxToRxSkew 50% 50% Figure 86. DATA and FLAG Signal Timing ...
Page 118
... MLB_CLK_P, MLB_SIG_P, and MLB_DATA_P. The O+ on MLB_CLK_N, MLB_SIG_N, and MLB_DATA_N. O- and and V are shorted together and/or shorted to ground < 50 mV. ID Min Max 1.0 1.5 - — 150 3 — 43 1.6 — 4 -50 50 -25 25 — -50 50 — 0.5 2.0 0.5 2.0 Freescale Semiconductor Unit V mV mVpp mA k ...
Page 119
... MLB_SIG/MLB_DATA receiver input hold from MLB_CLK low MLB_SIG/MLB_DATA output high impedance from MLB_CLK low Bus Hold from MLB_CLK low i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 78 and Table 79 lists the MediaLB 3-pin interface timing Figure 87. MediaLB 3-Pin Timing ...
Page 120
... Unit Comment MHz 1024xfs at 44.0 kHz 1024xfs at 50.0 kHz — ns (see — ns — — ns — — ns — ns (see mckl — ns — Figure 88 shows the MLB 6-pin Max Unit Comment 600 ps — 1.3 ns — 3.5 ns — Freescale Semiconductor ...
Page 121
... The PCIe interface complies with PCIe specification Gen2 x1 lane and supports the PCI Express 1.1/2.0 standard. 4.11.15.1 PCIE_REXT Reference Resistor Connection The impedance calibration process requires connection of reference resistor 200 1% precision resistor on PCIE_REXT pads to ground used for termination impedance calibration. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Symbol Min Max t 0.6 5 ...
Page 122
... The following subsections provide values obtained from a combination of simulations and silicon characterization. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 122 Table 81 lists the PWM timing parameters. Figure 89. PWM Timing Table 81. PWM Output Timing Parameters Min NOTE Max Unit ipg_clk MHz — ns — ns Freescale Semiconductor ...
Page 123
... SCAN JTAG Controller (SJC) Timing Parameters Figure 90 depicts the SJC test clock input timing. Figure 92 depicts the SJC test access port. Signal parameters are listed in JTAG_TCK (Input) SJ3 i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Symbol V CTM — Symbol V MIN_RX_EYE_HEIGHT PPM Figure 91 depicts the SJC boundary scan timing ...
Page 124
... Figure 92. Test Access Port Timing Diagram i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 124 SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid SJ8 Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid VIH SJ5 VIH SJ9 Freescale Semiconductor ...
Page 125
... Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode. i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor SJ13 Figure 93. JTAG_TRST_B Timing Diagram Table 84. JTAG Timing ...
Page 126
... V M Figure 94. SPDIF_SR_CLK Timing Diagram stclkp stclkpl V M Figure 95. SPDIF_ST_CLK Timing Diagram Timing Parameter Range Unit Min Max — 0.7 ns — 1.5 ns — 24.2 — 31.3 — 1.5 ns — 13.6 — 18.0 40.0 — ns 16.0 — ns 16.0 — ns 40.0 — ns 16.0 — ns 16.0 — ns srckph V M stclkph V M Freescale Semiconductor ...
Page 127
... AUDx_TXD (Output) AUDx_RXD (Input) Note: AUDx_RXD input in synchronous mode only Figure 96. SSI Transmitter Internal Clock Timing Diagram i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 86. Table 86. AUDMUX Port Allocation Type and Access SSI 1 SSI 2 AUD3 External – AUD3 I/O AUD4 External – ...
Page 128
... AC97 mode of operation). i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 128 Parameter Internal Clock Operation Synchronous Internal Clock Operation NOTE Min Max Unit 81.4 — ns 36.0 — ns 36.0 — ns — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 6.0 ns — 6.0 ns — 15.0 ns — 15.0 ns — 15.0 ns 10.0 — ns 0.0 — ns Freescale Semiconductor ...
Page 129
... SS11 AUDx_RXC high to AUDx_TXFS (wl) high SS13 AUDx_RXC high to AUDx_TXFS (wl) low SS20 AUDx_RXD setup time before AUDx_RXC low SS21 AUDx_RXD hold time after AUDx_RXC low i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 88 SS1 SS5 SS4 SS9 SS11 SS20 SS51 ...
Page 130
... For internal Frame Sync operation using external clock, the frame sync timing is same as that of transmit data (for example, during AC97 mode of operation). i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 130 Parameter Oversampling Clock Operation NOTE Min Max Unit 15.04 — ns 6.0 — ns — 3.0 ns 6.0 — ns — 3.0 ns Freescale Semiconductor ...
Page 131
... SS33 AUDx_TXC high to AUDx_TXFS (wl) low SS37 AUDx_TXC high to AUDx_TXD valid from high impedance SS38 AUDx_TXC high to AUDx_TXD high/low SS39 AUDx_TXC high to AUDx_TXD high impedance i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Table 89 SS22 SS25 SS26 SS29 SS31 SS37 SS38 ...
Page 132
... Figure 99. SSI Receiver External Clock Timing Diagram i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 132 Parameter Synchronous External Clock Operation NOTE Table 90 SS22 SS26 SS25 SS30 SS32 SS35 SS40 Min Max Unit 10.0 — ns 2.0 — ns — 6.0 ns lists the timing parameters for the SS24 SS34 SS41 SS36 Freescale Semiconductor ...
Page 133
... The terms, WL and BL, refer to Word Length (WL) and Bit Length(BL). • For internal Frame Sync operation using external clock, the frame sync timing is same as that of transmit data (for example, during AC97 mode of operation). i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Parameter External Clock Operation NOTE Electrical Characteristics Min ...
Page 134
... RTS from DTE to DCE Output CTS from DCE to DTE Input DTR from DTE to DCE Output DSR from DCE to DTE Output DCD from DCE to DTE Output RING from DCE to DTE Output Serial data from DCE to DTE Input Serial data from DTE to DCE Freescale Semiconductor ...
Page 135
... Receive Bit Time 1 The UART receiver can tolerate 1/(16 F exceed 3/(16 baud_rate Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. baud_rate i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor UA1 Bit 2 Bit 3 Bit 4 Bit 5 Symbol Min 1 t 1/F – ...
Page 136
... PARITY BIT Max 2 1 baud_rate ref_clk (3/16) (1 ref_clk baud_rate ref_clk Table 95 UA6 UA5 UA5 Bit 5 Bit 6 Bit 7 POSSIBLE PARITY BIT Max – 1/F + baud_rate 1/(16 baud_rate (5/16) (1/F ) baud_rate Freescale Semiconductor lists STOP BIT Unit — — lists STOP BIT Unit — — ...
Page 137
... The timings in the table are guaranteed when: —AC I/O voltage is between 0. the I/O supply —DDR_SEL configuration bits of the I/O are set to (10)b i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor NOTE Tstrobe Todelay Figure 104. USB HSIC Transmit Waveform Table 96. USB HSIC Transmit Parameters ...
Page 138
... On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification — Revision 2.0 plus errata and ecn June 4, 2010 • Battery Charging Specification (available from USB-IF) — Revision 1.2, December 7, 2010 i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 138 (On-The-Go and Embedded Host Supplement to the USB Freescale Semiconductor ...
Page 139
... EIM_DA4 EIM_DA5 EIM_DA6 EIM_DA7 EIM_DA8 EIM_DA9 EIM_DA10 EIM_DA11 EIM_DA12 EIM_DA13 EIM_DA14 EIM_DA15 EIM_A16 EIM_A17 i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Direction at Reset Boot Mode Selection Input Input 1 Boot Options Input Input Input Input Input Input Input Input Input ...
Page 140
... Table 99. Interfaces Allocation During Boot Allocated Pads During Boot eFuse Name BOOT_CFG3[2] BOOT_CFG3[3] BOOT_CFG3[4] BOOT_CFG3[5] BOOT_CFG3[6] BOOT_CFG3[7] BOOT_CFG4[0] BOOT_CFG4[1] BOOT_CFG4[2] BOOT_CFG4[3] BOOT_CFG4[4] BOOT_CFG4[5] BOOT_CFG4[6] BOOT_CFG4[7] Comment — — — — — Used for NOR, OneNAND boot Only CS0 is supported Freescale Semiconductor ...
Page 141
... SATA_TXM, SATA_TXP, SATA_RXP, SATA_RXM, SATA_REXT USB USB-OTG USB_OTG_DP PHY USB_OTG_DN USB_OTG_VBUS i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Allocated Pads During Boot Boot Mode Configuration Comment 8 bit Only CS0 is supported bit bit bit bit — ...
Page 142
... IMX 6 Series Signal Name Mapping (EB792). This list can be used to map the signal names used in older documentation to the new standardized naming conventions. 6 Package Information 6.2.1 Case FCPBGA mm, 0.8 mm Pitch Ball Matrix i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 142 Freescale Semiconductor ...
Page 143
... Lidded Package shows the top, bottom, and side views of the 21 21 mm lidded package. Figure 106 i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Package Information and Contact Assignments 143 ...
Page 144
... Package Information and Contact Assignments Figure 106 Lidded Package Top, Bottom, and Side Views i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 144 Freescale Semiconductor ...
Page 145
... HDMI_DDCCEC HDMI_VP HDMI_VPH NVCC_CSI NVCC_DRAM R18, T18, U18, V10, V11, V12, V13, NVCC_EIM0 NVCC_EIM1 NVCC_EIM2 NVCC_ENET NVCC_GPIO NVCC_JTAG NVCC_LCD i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Package Information and Contact Assignments Ball(s) Position(s) D4 AC2 V14, V15, V16, V17, V18, V9 ...
Page 146
... Primary supply for the SNVS regulator Secondary supply for the ARM0 and ARM1 cores (internal regulator output—requires capacitor if internal regulator is used) Primary supply for the ARM0 and ARM1 core regulator Freescale Semiconductor ...
Page 147
... VDD_HIGH_CAP CLK2_N C5 VDD_HIGH_CAP CLK2_P D5 VDD_HIGH_CAP CSI_CLK0M F4 NVCC_MIPI CSI_CLK0P F3 NVCC_MIPI i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Package Information and Contact Assignments Ball(s) Position(s) K9, L9, M9, N9, P9, R9, T9, U9 H10, J10 H9 AE17 Default Ball Type Mode Default Function (Reset Mode) ...
Page 148
... PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Freescale Semiconductor ...
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... AE13 NVCC_DRAM DRAM_A6 AC13 NVCC_DRAM DRAM_A7 Y13 NVCC_DRAM DRAM_A8 AB13 NVCC_DRAM i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition Default Ball Type Mode Default Function (Reset (Signal Name) Mode) GPIO ALT5 IPU1_DISP0_DATA11 ...
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... PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Freescale Semiconductor ...
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... AC3 NVCC_DRAM DRAM_DQM1 AC6 NVCC_DRAM DRAM_DQM2 AB8 NVCC_DRAM DRAM_DQM3 AE10 NVCC_DRAM i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition Default Ball Type Mode Default Function (Reset (Signal Name) Mode) DDR ALT0 DRAM_DATA38 ...
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... Output 0 Output 0 Output 0 Output 0 Input Hi-Z — — Input Hi-Z — — Output 0 Output 0 Input Hi-Z — — Input Hi-Z — — Input Hi-Z — — Input Hi-Z — — Input Hi-Z — — Input Hi-Z — — Input Hi-Z — — Input Hi-Z — — Output 0 — — Freescale Semiconductor ...
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... J19 NVCC_EIM0 EIM_D30 J20 NVCC_EIM0 EIM_D31 H21 NVCC_EIM0 EIM_DA0 L20 NVCC_EIM2 i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition Default Ball Type Mode Default Function (Reset (Signal Name) Mode) — — DSI_CLK_N — ...
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... Input PU (100K) Output 1 Output 1 Input PU (100K) Input PU (100K) Output 1 Output 1 Output 1 Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PD (100K) Input PU (100K) Input PU (100K) Freescale Semiconductor ...
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... NVCC_GPIO KEY_COL4 T6 NVCC_GPIO KEY_ROW0 V6 NVCC_GPIO KEY_ROW1 U6 NVCC_GPIO KEY_ROW2 W4 NVCC_GPIO i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition Default Ball Type Mode Default Function (Reset (Signal Name) Mode) GPIO ALT5 GPIO7_IO12 GPIO ALT5 ...
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... Input Keeper — — Input Keeper — — Input Keeper — — — — — — — — — — — — Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Freescale Semiconductor ...
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... B12 SATA_VPH SATA_TXP A12 SATA_VPH SD1_CLK D20 NVCC_SD1 SD1_CMD B21 NVCC_SD1 i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition Default Ball Type Mode Default Function (Reset (Signal Name) Mode) GPIO ALT5 NAND_DATA02 ...
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... PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PU (100K) Input PD (100K) Input PD (100K) — — — — — — Freescale Semiconductor ...
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... EIM_A19 EIM_A20 EIM_A21 EIM_A22 EIM_A23 EIM_A24 EIM_A25 EIM_DA0 EIM_DA1 EIM_DA2 EIM_DA3 i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition Default Ball Type Mode Default Function (Reset (Signal Name) Mode) — — USB_OTG_DN — ...
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... PD (100K) Input PD (100K) Input PD (100K) Input PD (100K) Input PD (100K) Input PD (100K) Input PD (100K) Input PD (100K) Input PD (100K) Input PD (100K) Input PD (100K) Input PD (100K) Input PD (100K) Input PD (100K) Output Drive state unknown (x) Output Drive state unknown (x) Output Drive state unknown (x) Freescale Semiconductor ...
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... Pitch Ball Map Table 103 shows the FCPBGA mm, 0.8 mm pitch ball map. Table 103 mm, 0.8 mm Pitch Ball Map i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Package Information and Contact Assignments 161 ...
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... Package Information and Contact Assignments Table 103 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 162 Freescale Semiconductor ...
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... Table 103 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Package Information and Contact Assignments 163 ...
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... Package Information and Contact Assignments Table 103 mm, 0.8 mm Pitch Ball Map (continued) i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 164 Freescale Semiconductor ...
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... Added Section 4.6.1, “XTALI and RTC_XTALI (Clock Inputs) DC • Section 4.10, “General-Purpose Media Interface (GPMI) i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 Freescale Semiconductor Substantive Change(s) added bulleted item regarding the SOC-level memory system. Sequence” updated wording. Modules” section updates. ...
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... Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited. ...