MCIMX6Q6AVT10AC Freescale Semiconductor, MCIMX6Q6AVT10AC Datasheet - Page 13

• Manufacturer Part Number: MCIMX6Q6AVT10AC
• Description: Processors - Application Specialized i.MX6Q
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6Q6AVT10AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.05 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FCBGA
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Freescale Semiconductor
OCOTP_CTRL OTP Controller
OSC 32 kHz
Mnemonic
MLB150
OCRAM
PWM-1
PWM-2
PWM-3
PWM-4
256 KB
MMDC
Block
16 KB
PCIe
PMU
RAM
RAM
LDB
LVDS Display Bridge Connectivity
MediaLB
Multi-Mode DDR
Controller
On-Chip Memory
Controller
OSC 32 kHz
PCI Express 2.0
Power-Management
Functions
Pulse Width
Modulation
Secure/non-secure
RAM
Internal RAM
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
Block Name
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Peripherals
Connectivity /
Multimedia
Peripherals
Connectivity
Peripherals
Security
Data Path
Clocking
Connectivity
Peripherals
Data Path
Connectivity
Peripherals
Secured
Internal
Memory
Internal
Memory
Subsystem
LVDS Display Bridge is used to connect the IPU (Image Processing Unit)
to External LVDS Display Interface. LDB supports two channels; each
channel has following signals:
Each signal pair contains LVDS special differential pad (PadP, PadM).
The MLB interface module provides a link to a MOST
using the standardized MediaLB protocol (up to 150 Mbps).
The module is backward compatible to MLB-50.
DDR Controller has the following features:
The On-Chip OTP controller (OCOTP_CTRL) provides an interface for
reading, programming, and/or overriding identification and control
information stored in on-chip fuse elements. The module supports
electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also
provides a set of volatile software-accessible signals that can be used for
software control of hardware elements, not requiring non-volatility. The
OCOTP_CTRL provides the primary user-visible mechanism for
interfacing with on-chip fuse elements. Among the uses for the fuses are
unique chip identifiers, mask revision numbers, cryptographic keys, JTAG
secure mode, boot characteristics, and various control signals, requiring
permanent non-volatility.
The On-Chip Memory controller (OCRAM) module is designed as an
interface between system’s AXI bus and internal (on-chip) SRAM
memory module.
In i.MX 6Dual/6Quad processors, the OCRAM is used for controlling the
256 KB multimedia RAM through a 64-bit AXI bus.
Generates 32.768 kHz clock from an external crystal.
The PCIe IP provides PCI Express Gen 2.0 functionality.
Integrated power management unit. Used to provide power to various
SoC domains.
The pulse-width modulator (PWM) has a 16-bit counter and is optimized
to generate sound from stored sample audio images and it can also
generate tones. It uses 16-bit resolution and a 4x16 data FIFO to
generate sound.
Secure/non-secure Internal RAM, interfaced through the CAAM.
Internal RAM, which is accessed through OCRAM memory controller.
• One clock pair
• Four data pairs
• Support 16/32/64-bit DDR3-1066 (LV) or LPDDR2-1066
• Supports both dual x32 for LPDDR2 and x64 DDR3 / LPDDR2
• Support up to 4 GByte DDR memory space
configurations (including 2x32 interleaved mode)
Brief Description
®
data network,
Modules List
13