MCIMX6L3DVN10AA Freescale Semiconductor, MCIMX6L3DVN10AA Datasheet - Page 12

• Manufacturer Part Number: MCIMX6L3DVN10AA
• Description: Processors - Application Specialized i.MX6 Megrez
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6L3DVN10AA

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 128 KB
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-432
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: 0 C
• Number Of Timers: 2

Modules List
12
Mnemonic
ROMCP
128 KB
RNGB
SDMA
Block
SNVS
96KB
ROM
RAM
PXP
SJC
PiXel Processing
Random Number
Memory Access
ROM Controller
System JTAG
Internal RAM
Block Name
Smart Direct
Non-Volatile
Boot ROM
Generator
with Patch
Controller
Pipeline
Storage
Secure
i.MX 6SoloLite Applications Processors for Consumer Products, Rev. 1
Table 2. i.MX 6SoloLite Modules List (continued)
Subsystem
Peripherals
Peripherals
Peripherals
Data Path
Memory
Memory
Security
Security
Internal
Internal
System
System
Control
Control
Display
A high-performance pixel processor capable of 1 pixel/clock performance for
combined operations, such as color-space conversion, alpha blending,
gamma-mapping, and rotation. The PXP is enhanced with features
specifically for gray scale applications. In addition, the PXP supports
traditional pixel/frame processing paths for still-image and video processing
applications, allowing it to interface with the integrated EPD. either of the
integrated EPD controllers.
Internal RAM, which is accessed through OCRAM memory controller.
Random number generating module.
Supports secure and regular Boot Modes. Includes read protection on 4K
region for content protection.
ROM Controller with ROM Patch support
The SDMA is multi-channel flexible DMA engine. It helps in maximizing
system performance by off-loading the various cores in dynamic data routing.
It has the following features:
The SJC provides JTAG interface, which complies with JTAG TAP standards,
to internal logic. The i.MX 6SoloLite processor uses JTAG port for production,
testing, and system debugging. In addition, the SJC provides BSR (Boundary
Scan Register) standard support, which complies with IEEE1149.1 and
IEEE1149.6 standards.
The JTAG port must be accessible during platform initial laboratory bring-up,
for manufacturing tests and troubleshooting, as well as for software
debugging by authorized entities. The i.MX 6SoloLite SJC incorporates three
security modes for protecting against unauthorized accesses. Modes are
selected through eFUSE configuration.
Secure Non-Volatile Storage, including Secure Real Time Clock, Security
State Machine, Master Key Control, and Violation/Tamper Detection and
reporting.
• Powered by a 16-bit Instruction-Set micro-RISC engine
• Multi-channel DMA supporting up to 32 time-division multiplexed DMA
• 48 events with total flexibility to trigger any combination of channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between ARM and SDMA
• Very fast Context-Softwareitching with 2-level priority based preemptive
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment, decrement,
• DMA ports can handle unit-directional and bi-directional flows (copy mode)
• Up to 8-word buffer for configurable burst transfers
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
channels
multi-tasking
and no address changes on source and destination address)
Brief Description
Freescale Semiconductor