MCIMX6L3DVN10AA Freescale Semiconductor, MCIMX6L3DVN10AA Datasheet - Page 35

• Manufacturer Part Number: MCIMX6L3DVN10AA
• Description: Processors - Application Specialized i.MX6 Megrez
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6L3DVN10AA

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 128 KB
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-432
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: 0 C
• Number Of Timers: 2

1
2
3
4
4.6.3
The DDR I/O pads support LPDDR2 and DDR3 operational modes.
4.6.3.1
The LPDDR2 interface mode fully complies with JESD209-2B LPDDR2 JEDEC standard release June,
2009. The parameters in
noted.
1
2
Freescale Semiconductor
Sink current in Open Drain mode
Sink/source current in Push-Pull
mode
High-level output voltage
Low-level output voltage
Input reference voltage
DC input High Voltage
DC input Low Voltage
Differential Input Logic High
Differential Input Logic Low
Input current (no pull-up/down)
Pull-up/pull-down impedance Mismatch
240 Ω unit calibration resolution
Keeper circuit resistance
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.
Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
DSE is the Drive Strength Field setting in the associated IOMUX control register.
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot (see
Parameter
DDR I/O DC Parameters
LPDDR2 Mode I/O DC Parameters
Parameters
i.MX 6SoloLite Applications Processors for Consumer Products, Rev. 1
Table 23
Symbol
Table 23. LPDDR2 I/O DC Electrical Parameters
Table 22. GPIO I/O DC Parameters (continued)
Iskod
Isspp
are guaranteed per the operating ranges in
MMpupd
Symbol
Vih(diff)
Vih(dc)
Vil(diff)
Vil(dc)
Rkeep
Rres
Vref
Voh
Vol
Iin
Table
Test Conditions
27).
Test Conditions
Vin = 0 or OVDD
Ioh = -0.1 mA
Iol = 0.1 mA
—
—
—
—
—
0.49*OVDD
Vref+0.13V
See Note
0.9*OVDD
OVSS
0.26
Min
-2.5
110
-15
—
1
Table
Min
2
—
—
Electrical Characteristics
9, unless otherwise
0.51*OVDD
Vref-0.13V
See Note
0.1*OVDD
OVDD
-0.26
Max
+15
175
2.5
10
—
Max
7
7
2
Unit
Unit
μA
kΩ
mA
mA
%
Ω
V
V
V
V
35