MCIMX6U6AVM08ABR Freescale Semiconductor, MCIMX6U6AVM08ABR Datasheet - Page 13
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MCIMX6U6AVM08ABR
Manufacturer Part Number
MCIMX6U6AVM08ABR
Description
Processors - Application Specialized i.MX6 DualLite
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX6S6AVM08ABR.pdf
(174 pages)
Specifications of MCIMX6U6AVM08ABR
Rohs
yes
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
800 MHz
Data Ram Size
16 KB
Operating Supply Voltage
1.175 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
MAPBGA-624
Interface Type
Parallel
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
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Freescale Semiconductor
Block Mnemonic
512x8 Fuse Box
GPU3Dv5
GPU2Dv2
HDMI Tx
GPIO-1
GPIO-2
GPIO-3
GPIO-4
GPIO-5
GPIO-6
GPIO-7
GPMI
I
I
I
I
GPT
2
2
2
2
HSI
C-1
C-2
C-3
C-4
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
General Media Interface
General Purpose Timer
Electrical Fuse Array
General Purpose I/O
Graphics Processing
Graphics Processing
Unit-2D, ver 2
Block Name
I
MIPI HSI i/f
HDMI Tx i/f
2
Unit, ver.5
C Interface
Modules
Table 2. i.MX 6Solo/6DualLite Modules List (continued)
Timer Peripherals
System Control
Subsystem
Connectivity
Connectivity
Connectivity
Peripherals
Peripherals
Peripherals
Peripherals
Peripherals
Peripherals
Peripherals
Multimedia
Multimedia
Multimedia
Security
Electrical Fuse Array. Enables to setup Boot Modes,
Security Levels, Security Keys, and many other system
parameters.
The i.MX 6Solo/6DualLite processors consist of
512x8-bit fuse fox accessible through OCOTP_CTRL
interface.
Used for general purpose input/output to external ICs.
Each GPIO module supports 32 bits of I/O.
The GPMI module supports up to 8x NAND devices.
40-bit ECC encryption/decryption for NAND Flash
controller (GPMI2). The GPMI supports separate DMA
channels per NAND device.
Each GPT is a 32-bit “free-running” or “set and forget”
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
The GPU3Dv5 provides hardware acceleration for 3D
graphics algorithms with sufficient processor power to
run desktop quality interactive graphics applications on
displays up to HD1080 resolution. The GPU3D provides
OpenGL ES 2.0, including extensions, OpenGL ES 1.1,
and OpenVG 1.1
The GPU2Dv2 provides hardware acceleration for 2D
graphics algorithms, such as Bit BLT, stretch BLT, and
many other 2D functions.
The HDMI module provides HDMI standard i/f port to an
HDMI 1.4 compliant display.
The MIPI HSI provides a standard MIPI interface to the
applications processor.
I
rates of up to 400 kbps are supported.
2
C provide serial interface for external devices. Data
Brief Description
Modules List
13
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