MAX5165NECM Maxim Integrated, MAX5165NECM Datasheet - Page 6

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MAX5165NECM

Manufacturer Part Number
MAX5165NECM
Description
Sample & Hold Amplifiers
Manufacturer
Maxim Integrated
Series
MAX5165r
Datasheet

Specifications of MAX5165NECM

Number Of Channels
32
Acquisition Time
4 us
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
TQFP-48
Minimum Dual Supply Voltage
- 4.75 V, + 9.5 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MAX5165NECM+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
MAX5165NECM+T
Manufacturer:
Maxim Integrated
Quantity:
10 000
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
The MAX5166 connects four separate analog inputs to
four internal 1-to-8 analog multiplexers. Each multiplex-
er channel connects to a buffered sample/hold circuit
and a series output resistor, creating a four-input
device with 32 sample/hold output channels. Three
multiplexer channel-address inputs and four mode-
select inputs (one for each multiplexer) control channel
selection and sample/hold functions (Figure 1 and
Tables 1 and 2).
Three address pins and 3-to-8 address decoder logic
select the channel for all four internal analog multiplex-
ers. The mode-select inputs (M3–M0) independently
control the sample/hold functions for each multiplexer
(Tables 1 and 2).
The MAX5166 contains 32 buffered sample/hold cir-
cuits with internal hold capacitors. Internal hold capaci-
tors minimize leakage current, dielectric absorption,
feedthrough, and required board space. The value of
the hold capacitor affects acquisition time, hold step,
and droop rate. Lower capacitance allows faster acqui-
6
_______________Detailed Description
_________________________________________________________________________________________
1, 47, 48
10–13
14–29
31–46
_______________________________________________________________________________________
PIN
2–5
30
6
7
8
9
OUT16–OUT31
OUT0–OUT15
A2, A0, A1
IN3–IN0
M0–M3
NAME
DGND
AGND
V
V
V
DD
SS
L
Address Inputs. The input of a 3-to-8 decoder that controls channel selection for all four 1-to-8
multiplexers. Selects which output channels are connected to the input during sample mode
(Tables 1, 2).
Mode-Selection/Multiplexer-Enable Inputs 0 to 3. All four 1-to-8 multiplexers are independently
controlled. A logic low enables sample mode by connecting the selected channel to IN_. A logic
high enables hold mode (Tables 1, 2).
Positive Digital Logic Power-Supply Input
Digital Ground
Negative Analog Power-Supply Input
Analog Ground
Analog Inputs 0 to 3
Outputs 0 to 15
Positive Analog Power-Supply Input
Outputs 16 to 31
Digital Interface
Sample/Hold
sition times but increases the droop rate. Higher values
increase hold time and acquisition time. The hold
capacitor used in the MAX5166 provides fast 2.5µs
(typ) acquisition time while maintaining a low 1mV/sec
(typ) droop rate, making the sample/hold ideal for high-
speed sampling.
Driving M3–M0 low (one at a time) selects sample
mode (Tables 1 and 2). During sample mode, the
selected multiplexer channel connects to IN_ allowing
the hold capacitor to acquire the input signal. To guar-
antee an accurate sample, maintain sample mode for
at least 4µs. Sampling for longer than 4µs results in
tracking. Only the addressed channel on the selected
multiplexer samples the input; all other channels remain
in hold mode.
Driving M3–M0 high selects hold mode. Hold mode dis-
ables the multiplexer, which disconnects all eight chan-
nels on the 1-to-8 multiplexer from the input. When a
channel is disconnected, the hold capacitor maintains
the sampled voltage at the output with a 1mV/sec
droop rate (towards V
FUNCTION
DD
).
Pin Description
Sample Mode
Hold Mode

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