MAX5165NECM Maxim Integrated, MAX5165NECM Datasheet - Page 7

• Manufacturer Part Number: MAX5165NECM
• Description: Sample & Hold Amplifiers
• Manufacturer: Maxim Integrated
• Series: MAX5165r

Specifications of MAX5165NECM

• Number Of Channels: 32
• Acquisition Time: 4 us
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Minimum Dual Supply Voltage: - 4.75 V, + 9.5 V

Table 1. Output Selection
0 = Logic Low, 1 = Logic High
Table 2. Mode Selection
0 = Logic Low, 1 = Logic High
* Only one M_ input asserted low; all others must be logic high
to meet the timing specification (see Single vs. Simultaneous
Sampling).
When switching between sample mode and hold
mode, the voltage of the hold capacitor changes due to
charge injection from stray capacitance. This voltage
change, called hold step, is minimized by limiting the
amount of stray capacitance seen by the hold capaci-
tor. The MAX5166 limits the hold step to 0.25mV (typ).
An output capacitor to ground can be used to filter out
this small hold-step error.
The MAX5166 contains an output buffer for each multi-
plexer channel (32 total), so the hold capacitor sees a
high-impedance input, reducing the droop rate. While
in hold mode, the hold capacitor discharges at a rate of
1mV/sec (typ). The buffer also provides a low output
impedance; however, the device contains output resis-
tors in series with the buffer output (Figure 1) for select-
ed output filtering. To provide greater design flexibility,
the MAX5166 is available with an R
1kΩ.
INPUTS* (M3–M0)
MODE-SELECT
A2
0
0
0
0
1
1
1
1
0
1
ADDRESS
_______________________________________________________________________________________
A1
0
0
1
1
0
0
1
1
Sample mode enabled on selected
analog multiplexer and channel
(Table 1).
Hold mode enabled on selected
analog multiplexer and channel
(Table 1).
32-Channel Sample/Hold Amplifier
ACTION
A0
0
1
0
1
0
1
0
1
O
of 50Ω, 500Ω, or
Hold Step
with Four Multiplexed Inputs
Output
MUX0
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Note: Output loads increase the analog supply cur-
rent (I
damages the device by consuming more power than
the device will dissipate (see Absolute Maximum
Ratings). The resistor-divider formed by the output
resistor (R
sampled voltage (V
age (V
The maximum output voltage range depends on the
analog supply voltages available and the scaling factor
used:
when R
(V
Acquisition time (t
MAX5166 must remain in sample mode for the hold
capacitor to acquire an accurate sample. The hold-
mode settling time (t
for the output voltage to settle to its final value.
Aperture delay (t
connect the input from the hold capacitor. The inhibit
pulse width (t
must remain in hold mode while the address is
changed. The data setup time (t
time an address must be maintained before the
address becomes valid. The data hold time (t
amount of time an address must be maintained after
mode select has gone from low to high (Figure 2).
SS
(V
+ 0.75V) ≤ V
DD
OUT_
SS
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
L
MUX1
OUT8
OUT9
= ∞, then A
Voltage Gain = A
+ 0.75V) · A
OUTPUT SELECTED
and I
OUT_
) as follows:
PW
SS
) and load impedance (R
AP
) is the amount of time the MAX5166
OUT
V
). Excessive loading of the output(s)
OUT_
) is the time interval required to dis-
SAMP
H
V
AQ
V
) is the amount of time necessary
≤ (V
= 1, and this equation becomes
≤ V
) is the amount of time the
= V
OUT16
OUT17
OUT18
OUT19
OUT20
OUT21
OUT22
OUT23
). Determine the output volt-
MUX2
DD
V
OUT_
SAMP
= R
- 2.4V).
Timing Definitions
L
≤ (V
/(R
· A
DS
L
DD
V
) is the amount of
+ R
- 2.4V) · A
OUT
L
) scales the
OUT24
OUT25
OUT26
OUT27
OUT28
OUT29
OUT30
OUT31
MUX3
)
DH
) is the
V
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