70T3539MS133BC IDT, 70T3539MS133BC Datasheet - Page 15

• Manufacturer Part Number: 70T3539MS133BC
• Description: SRAM 512K X 36 STD-PWR, 2.5V DUAL PORT RAM
• Manufacturer: IDT
• Series: IDT70T3539Mr
• Type: Dual Port RAMr

Specifications of 70T3539MS133BC

• Memory Size: 18 Mbit
• Organization: 512 K x 36
• Access Time: 4.2 ns
• Supply Voltage - Max: 2.6 V
• Supply Voltage - Min: 2.4 V
• Maximum Operating Current: 740 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-256
• Interface: LVTTL
• Maximum Clock Frequency: 133 MHz
• Memory Type: Synchronous
• Part # Aliases: IDT70T3539MS133BC

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = V
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE
3. Addresses do not have to be accessed sequentially since ADS = V
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
reference use only.
ADDRESS
0
DATA
ADDRESS
, BEn, and ADS = V
DATA
DATA
DATA
CLK
R/
CE
CE
BEn
OUT
CLK
R/
CE
CE
BEn
OUT
W
IN
OE
0
1
W
IN
(3)
0
1
(3)
(1)
(1)
t
t
t
t
IL
SB
SW
SC
SA
t
t
t
t
; CE
SB
SW
SC
SA
An
An
t
t
t
1
t
HC
HW
HA
, CNTEN, and REPEAT = V
HB
t
t
t
t
t
HW
HC
HB
HA
t
CH1
CD1
t
t
CH1
CD1
t
CYC1
t
CYC1
READ
READ
t
CL1
t
Qn
CL1
Qn
An +1
An +1
t
DC
t
DC
t
CD1
t
IH
OHZ
.
Qn + 1
t
An + 2
t
SW
SD
IL
An + 2
Dn + 2
constantly loads the address on the rising edge of the CLK; numbers are for
t
t
HD
HW
6.42
NOP
15
t
CKHZ
(5)
t
t
WRITE
SW
SD
Dn + 2
An + 2
An + 3
Dn + 3
t
t
HD
HW
WRITE
Industrial and Commercial Temperature Ranges
An + 3
An + 4
t
CKLZ
t
OE
t
CD1
t
CD1
t
CKLZ
READ
Qn + 3
READ
Qn + 4
An + 4
An + 5
t
DC
t
DC
t
t
CD1
CD1
5678 drw 13
5678 drw 14
IL
)
(2)
,
,
(2)