70T3539MS133BC IDT, 70T3539MS133BC Datasheet - Page 19

• Manufacturer Part Number: 70T3539MS133BC
• Description: SRAM 512K X 36 STD-PWR, 2.5V DUAL PORT RAM
• Manufacturer: IDT
• Series: IDT70T3539Mr
• Type: Dual Port RAMr

Specifications of 70T3539MS133BC

• Memory Size: 18 Mbit
• Organization: 512 K x 36
• Access Time: 4.2 ns
• Supply Voltage - Max: 2.6 V
• Supply Voltage - Min: 2.4 V
• Maximum Operating Current: 740 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-256
• Interface: LVTTL
• Maximum Clock Frequency: 133 MHz
• Memory Type: Synchronous
• Part # Aliases: IDT70T3539MS133BC

Truth Table IV — Collision Detection Flag
Waveform of Collision Timing
Collision Detection Timing
NOTES:
1. CE
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
NOTES:
1. CE
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3t
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
CLK
↑
↑
↑
↑
0 =
0
L
ADDRESS
Cycle Time
= V
ADDRESS
V
7.5ns
IL
5ns
6ns
IL
, CE
and CE
R/W
COL
COL
CLK
CLK
H
H
L
L
1
L
R
(1)
= V
L
(4)
R
(4)
R
1 =
L
L
IH
V
.
IH
Left Port
CE
. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
L
L
L
L
L
(1)
Region 1 (ns)
t
SA
A
0 - 2.8
0 - 3.8
0 - 5.3
0
t
SA
t
A
HA
18L
MATCH
MATCH
MATCH
MATCH
A
-A
0
t
t
CYC
OFS
HA
0L
(2)
2
(1)
+ t
t
OFS
COLS
COL
(ns)
A
after Address match.
H
L
H
L
1
L
Region 2 (ns)
A
(3,4)
2.81 - 4.6
3.81 - 5.6
5.31 - 7.1
1
CLK
(1,2)
↑
↑
↑
↑
R
5678 tbl 13
(2)
A
2
R/W
6.42
H
L
H
L
A
R
19
(1)
2
t
OFS
NOTES:
1. Region 1
2. Region 2
3. All the production units are tested to midpoint of each region.
4. These ranges are based on characterization of a typical device.
t
COLS
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
Right Port
CE
L
L
L
L
R
(1)
A
3
A
t
COLS
A
3
t
COLR
18R
MATCH
MATCH
MATCH
MATCH
-A
Industrial and Commercial Temperature Ranges
0R
(2)
(3)
t
COL
COLR
H
H
L
L
R
Both ports reading. Not a valid collision.
No flag output on either port.
Left port reading, Right port writing.
Right port reading, Left port writing.
Both ports writing. Valid collision. Flag
output on both ports.
Valid collision, flag output on Left port.
Valid collision, flag output on Right port.
Function
5678 drw 20
5678 tbl 14