71V416S10PHG IDT, 71V416S10PHG Datasheet
71V416S10PHG
Specifications of 71V416S10PHG
Related parts for 71V416S10PHG
71V416S10PHG Summary of contents
Page 1
... IDT71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a 44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x 9mm package. ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Pin Configurations - SOJ/TSOP SO44 SO44 *Pin 28 can either connected to Vss ...
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... Supply Voltage DD V Ground SS V Input High Voltage IH V Input Low Voltage IL NOTES: 1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle. I/O I/O I/O I/O BHE High-Z High-Z ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) DC Electrical Characteristics (V = Min. to Max., Commercial and Industrial Temperature Ranges) DD Symbol Parameter |I | Input Leakage Current Output Leakage Current LO V Output Low Voltage OL V Output High Voltage OH DC Electrical Characteristics (V = Min. to Max 0.2V ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) AC Electrical Characteristics (V = Min. to Max., Commercial and Industrial Temperature Ranges) DD Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Select Access Time ACS (1) t Chip Select Low to Output in Low-Z CLZ ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Timing Waveform of Read Cycle No. 2 ADDRESS OE CS BHE, BLE DATA OUT NOTES HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise t 3. Transition is measured ±200mV from steady state. ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Timing Waveform of Write Cycle No. 2 (CS Controlled Timing) ADDRESS BHE, BLE WE DATA OUT DATA IN Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing) ADDRESS BHE, BLE WE DATA OUT DATA IN NOTES write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. ...
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... IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Ordering Information 71V416 X XX Device Power Speed Package Type X XXX X Process/ Temperature Range 6.42 8 Commercial and Industrial Temperature Ranges X Blank Tube or Tray 8 Tape and Reel Blank Commercial (0°C to +70°C) I Industrial (-40°C to +85°C) ...
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... Pg. 8 Removed die revision information from the Ordering Information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Commercial and Industrial Temperature Ranges on Write Cycle No. 1 diagram CW for SALES: 800-345-7015 or ...