71V416S10PHG IDT, 71V416S10PHG Datasheet - Page 7

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71V416S10PHG

Manufacturer Part Number
71V416S10PHG
Description
SRAM 256Kx16 ASYNCHRONOUS 3.3V CMOS SRAM
Manufacturer
IDT
Datasheet

Specifications of 71V416S10PHG

Rohs
yes
Memory Size
4 Mbit
Organization
256 K x 16
Access Time
10 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
Maximum Operating Current
200 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TSOP-44
Part # Aliases
IDT71V416S10PHG
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
Timing Waveform of Write Cycle No. 3
(BHE, BLE Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. During this period, I/O pins are in the output state, and input signals must not be applied.
3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
DATA
ADDRESS
ADDRESS
DATA
BHE, BLE
BHE, BLE
DATA
DATA
OUT
WE
OUT
WE
CS
CS
IN
IN
t
AS
t
AS
(1,3)
t
t
AW
AW
t
CW
t
t
WP
WP
(2)
t
t
t
WC
BW
WC
6.42
t
CW
7
(2)
t
BW
DATA
t
t
DATA
DW
DW
IN
IN
VALID
VALID
Commercial and Industrial Temperature Ranges
t
t
DH
DH
t
t
WR
WR
(1,3)
3624 drw 10
3624 drw 09

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