5962-8855201XA IDT, 5962-8855201XA Datasheet - Page 8

• Manufacturer Part Number: 5962-8855201XA
• Description: SRAM
• Manufacturer: IDT

Specifications of 5962-8855201XA

• Memory Size: 256 KB
• Organization: 32 K x 8
• Access Time: 20 ns
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Maximum Operating Current: 150 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: Through Hole
• Package / Case: CDIP-28
• Memory Type: CMOS

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. t
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
ADDRESS
ADDRESS
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
DATA
DATA
on the bus for the required t
as the specified t
WR
DATA
is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
CS
WE
OUT
WE
OE
IN
CS
IN
WP
. For a CS controlled write cycle, OE may be LOW with no degradation to t
DW
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short
t
t
AS
AS
(3)
t
WZ
(5)
t
t
AW
AW
t
WP
t
t
CW
WC
t
(6)
WC
(6)
8
Military, Commercial, and Industrial Temperature Ranges
WP
t
DW
t
or (t
DW
CW
WHZ
.
+t
DW
) to allow the I/O drivers to turn off and data to be placed
t
DH
t
WR
t
t
WR
t
OW
t
DH2
(1,2,4)
(1,2,4,6)
t
OHZ
(5)
(3)
2946 drw 10
2946 drw 11