AS7C1024B-12TJIN Alliance Memory, AS7C1024B-12TJIN Datasheet - Page 6
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AS7C1024B-12TJIN
Manufacturer Part Number
AS7C1024B-12TJIN
Description
SRAM 1M, 5V, 12ns FAST 128K x 8 Asynch SRAM
Manufacturer
Alliance Memory
Datasheet
1.AS7C1024B-15TJCN.pdf
(9 pages)
Specifications of AS7C1024B-12TJIN
Rohs
yes
Memory Size
1 Mbit
Organization
128 Kbit x 8
Access Time
12 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Maximum Operating Current
100 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOJ-32
Memory Type
CMOS
Factory Pack Quantity
22
Write waveform 2 (CE1 and CE2 controlled)
AC test conditions
Notes
1
2
3
4
5
6
7
8
9
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
Address
3/26/04, v 1.2
During V
This parameter is sampled and not 100% tested.
For test conditions, see AC Test Conditions, Figures A and B.
t
This parameter is guaranteed, but not 100% tested.
WE is high for read cycle.
CE1 and OE are low and CE2 is high for read cycle.
Address valid prior to or coincident with CE1 transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
D
CLZ
CE1
CE2
– Output load: see Figure B.
– Input pulse level: GND to 3.5V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
OUT
WE
D
IN
+3.5V
and t
GND
CC
CHZ
power-up, a pull-up resistor to V
are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.
10%
Figure A: Input pulse
90%
2 ns
t
AS
90%
10%
CC
on CE1 is required to meet I
t
WZ
Alliance Memory Inc.
t
AW
Figure B: 5V Output load
t
D
CW1
OUT
255Ω
, t
t
t
WP
WC
CW2
10,11,12
t
Data valid
DW
+5V
480Ω
C
GND
SB
13
specification.
®
t
t
WR
AH
t
DH
D
OUT
Thevenin equivalent:
168Ω
+1.728V
AS7C1024B
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