70T3339S200BC IDT, 70T3339S200BC Datasheet

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... L NOTES: 1. Address for the IDT70T3319. Also, Addresses The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. ...

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... CE and CE permits the on-chip circuitry of each port enter a very low standby power mode. The IDT70T3339/19/99 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device ( 2.5V. ...

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... T1 T4 TCK (2) 17R NOTES: 1. Pin for IDT70T3319 and IDT70T3399. 2. Pin for IDT70T3399. 3. All V pins must be connected to 2.5V power supply All V pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DDQ set to V (0V). ...

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... PIPE/ FT INT NOTES: 1. Pin for IDT70T3319 and IDT70T3399. 2. Pin for IDT70T3399. 3. All V pins must be connected to 2.5V power supply All V pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DDQ set to V (0V). ...

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... I/Os and controls will operate at 3.3V DD must be supplied at 3.3V. If OPT is set asserted, the counter will reset to the last valid address loaded for the IDT70T3319. Also, Addresses A (0V), then that must be DDQX and A are 18x 17x , i ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Truth Table I—Read/Write and Enable Control CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ...

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... Input High Voltage - ZZ, OPT, PIPE/FT (1) Input Low Voltage -0.3 IL Input Low Voltage - (1) -0.3 IL ZZ, OPT, PIPE/FT (min.) = -1.0V for pulse width less than t /2, or 5ns, whichever is less. IL CYC (max 1.0V for pulse width less than t IH DDQ (2.5V), and V DD DDQX 6.42 7 Industrial and Commercial Temperature Ranges (1) ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Absolute Maximum Ratings Symbol Rating V V Terminal Voltage TERM with Respect to GND DD ( Terminal Voltage TERM DDQ (V ) with Respect to GND DDQ V (2) Input and I/O Terminal TERM (INPUTS and I/O's) Voltage with Respect to GND ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating DD L Current (Both Outputs Disabled, (1) Ports Active MAX (6) Standby Current SB1 L (1) (Both Ports - TTL ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM AC Test Conditions (V Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT ∆ tCD (Typical, ns) - 3.3V/2.5V) DDQ GND to 3 0V/GND to 2.4V . GND to 3.0V/GND to 2.4V 2ns 1 ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol (1) t Clock Cycle Time (Flow-Through) CYC1 (1) t Clock Cycle Time (Pipelined) CYC2 (1) t Clock High Time (Flow-Through) CH1 (1) t Clock Low Time (Flow-Through) ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Timing Waveform of Read Cycle for Pipelined Operation (2) (FT/PIPE = CH2 CLK UB (4) ADDRESS An (1 Latency) DATA OUT (1) OE Timing Waveform of Read Cycle for Flow-through Output ...

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... ADDRESS 0 (B2) CE 0(B2 DATA OUT(B2) NOTES Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3339/19/99 for this waveform, and are setup for depth expansion in this example. ADDRESS 2. UB, LB, OE, and ADS = 1(B1) 1(B2 ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Timing Waveform of Left Port Write to Pipelined Right Port Read CLK "A" R/W "A " ADDRESS "A" MATC DATA VALID IN"A" t CLK "B" R/W "B" ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Timing Waveform of Pipelined Read-to-Write-to-Read (2) ( CYC2 t CH2 CLK UB (3) An ADDRESS DATA IN DATA OUT NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Timing Waveform of Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK UB (3) An ADDRESS DATA IN t CD1 (1) DATA OUT READ Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled) ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Timing Waveform of Pipelined Read with Address Counter Advance t CYC2 t CH2 CLK ADDRESS SAD HAD ADS CNTEN ( DATA OUT READ EXTERNAL ADDRESS Timing Waveform of Flow-Through Read with Address Counter Advance ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs) t CYC2 t CH2 CLK ADDRESS (3) INTERNAL ADDRESS t t SAD HAD ADS CNTEN DATA IN WRITE EXTERNAL ADDRESS Timing Waveform of Counter Repeat ...

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... R/W and CE are synchronous with respect to the clock and need valid set-up and hold times A18 for IDT70T3319, therefore Interrupt Addresses are 3FFFF and 3FFFE A18 and A17 are NC's for IDT70T3399, therefore Interrupt Addresses are 1FFFF and 1FFFE ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Waveform of Collision Timing Both Ports Writing with Left Port Clock Leading CLK L t OFS ( ADDRESS L COL L CLK (4) ADDRESS COL R NOTES For reading port Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases. ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Timing Waveform - Entering Sleep Mode R/W Timing Waveform - Exiting Sleep Mode R/W OE DATA OUT (4) NOTES IH. 2. All timing is same for Left and Right ports has to be deactivated ( three cycles prior to asserting ZZ (ZZx = V ...

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... SRAM location. If the interrupt function is not used, address locations 7FFFE and 7FFFF (3FFFF or 3FFFE for IDT70T3319 and 1FFFF or 1FFFE for IDT70T3399) are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. ...

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... Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT70T3339/19/99 can also be used in applications requiring expanded width, as indicated in Figure 4. Through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 36-bits or wider. ...

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... IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM JTAG Timing Specifications t JF TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO TRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO. JTAG AC Electrical Characteristics ...

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... NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com contacting your local IDT sales representative. Value ...

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... NOTES: 1. 166MHz I-Temp is not available in the BF-208 package. 2. 200Mhz is not available in the BF-208 package. 3. Green parts available. For specific speeds, packages and powers contact your local sales office. IDT Clock Solution for IDT70T3339/19/99 Dual-Port Dual-Port I/O Specitications IDT Dual-Port Part Number Voltage 70T3339/19/99 2 ...

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... Removed the DD 144-pin TQFP (DD-144) Thin Quad Flatpack per PDN: F-08-01 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. and t specs in AC Electrical Characteristics table INR symbol and parameter to AC Electrical Characteristics table ...