70T3339S200BC IDT, 70T3339S200BC Datasheet - Page 21

• Manufacturer Part Number: 70T3339S200BC
• Description: SRAM
• Manufacturer: IDT

Specifications of 70T3339S200BC

• Part # Aliases: IDT70T3339S200BC

Timing Waveform - Entering Sleep Mode
Timing Waveform - Exiting Sleep Mode
NOTES:
1. CE
2. All timing is same for Left and Right ports.
3. CE
4. CE
5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
1 =
0
0
has to be deactivated (CE
has to be deactivated (CE
V
IH.
DATA
R/W
R/W
OE
OUT
0
0
= V
= V
(4)
IH
IH
) three cycles prior to asserting ZZ (ZZx = V
) one cycle prior to de-asserting ZZ (ZZx = V
6.42
21
(5)
IH
IL
(1,2)
) and held for two cycles after asserting ZZ (ZZx = V
) and held for three cycles after de-asserting ZZ (ZZx = V
(1,2)
(3)
Industrial and Commercial Temperature Ranges
An
(5)
An+1
Dn
IH
).
IL
Dn+1
).