CY7C1412KV18-333BZXI Cypress Semiconductor, CY7C1412KV18-333BZXI Datasheet
CY7C1412KV18-333BZXI
Specifications of CY7C1412KV18-333BZXI
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CY7C1412KV18-333BZXI Summary of contents
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... To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 9-bit words (CY7C1425KV18), 18-bit words (CY7C1412KV18), or 36-bit words (CY7C1414KV18) that burst sequentially into or out of the device. Because data can be transferred into and out of ...
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... Logic Block Diagram – CY7C1425KV18 9 D [8:0] 21 Address A (20:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [0] Logic Block Diagram – CY7C1412KV18 18 D [17:0] 20 Address A (19:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 Write Write Address ...
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... Logic Block Diagram – CY7C1414KV18 36 D [35:0] 19 Address A (18:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 Write Write Address Reg Reg Register Control Logic Read Data Reg Reg. Reg. 36 Reg. CY7C1425KV18 19 A (18:0) RPS ...
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... TAP Controller Block Diagram ...................................... 16 TAP Electrical Characteristics ...................................... 16 TAP AC Switching Characteristics ............................... 17 TAP Timing and Test Conditions .................................. 18 Identification Register Definitions ................................ 19 Document Number: 001-57825 Rev. *F CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Scan Register Sizes ....................................................... 19 Instruction Codes ........................................................... 19 Boundary Scan Order .................................................... 20 Power Up Sequence in QDR II SRAM ........................... 21 Power Up Sequence ................................................. 21 PLL Constraints ......................................................... 21 Maximum Ratings ...
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... Pin Configurations The pin configurations for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow NC/72M DOFF V V REF DDQ ...
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... Pin Configurations (continued) The pin configurations for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow NC/144M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 ...
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... Internally, the device is organized × arrays each × 9) for CY7C1425KV18 × arrays each × 18) for CY7C1412KV18, and 1 M × arrays each of 512 K × 36) for CY7C1414KV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1425KV18, 20 address inputs for CY7C1412KV18, and 19 address inputs for CY7C1414KV18 ...
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... DD V Ground Ground for the device Power supply Power supply inputs for the outputs of the device. DDQ Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 Pin Description output impedance are set to 0.2 × RQ, where resistor [x:0] CY7C1425KV18 , which enables the DDQ Page ...
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... K clock rise. [x:0] Depth Expansion The CY7C1412KV18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port ...
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... Delayed 50ohms Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 However not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 s after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in QDR I mode (with one cycle latency and a longer access time) ...
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... Truth Table The truth table for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow. Operation Write cycle: Load address on the rising edge of K; input write data on K and K rising edges. Read cycle: Load address on the rising edge of K; wait one and a half cycle; read data on C and C rising edges. ...
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... Is based on a write cycle that was initiated in accordance with the of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 [9, 10] Comments [9, 11] K – ...
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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 Instruction Register Three-bit instructions are serially loaded into the instruction register. This register is loaded when it is placed between the TDI ...
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... Document Number: 001-57825 Rev. *F CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins ...
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... TAP Controller State Diagram The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 [12] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- ...
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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 14. Overshoot: V < 0.85 V (Pulse width less than t IH(AC) DDQ 15. All voltage referenced to Ground. Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 0 Bypass Register Instruction Register ...
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... TDOX Notes 16. t and t refer to the setup and hold time requirements of latching data from the boundary scan register 17. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 Description / ns CY7C1425KV18 Min Max ...
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... Test Clock TCK Test Mode Select TMS Test Data In TDI Test Data Out TDO Note 18. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 [18] Figure 3. TAP Timing and Test Conditions 0.9V 50 ...
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... TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Description CY7C1414KV18 000 Version number. 11010011010100111 Defines the type of SRAM ...
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... CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Bump ID Bit # 100 ...
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... DDQ DOFF Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 PLL Constraints PLL uses K clock as its synchronizing input. The input must ■ have low phase jitter, which is specified as t The PLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the PLL is enabled, then the ■ ...
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... Output are impedance controlled DDQ 23. Output are impedance controlled DDQ whichever is larger, V REF(min) DDQ Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 Operating Range Range Commercial Industrial Neutron Soft Error Immunity Parameter DD + 0.5 V DDQ LSBU + 0 LMBU SEL * No LMBU or SEL events occurred during testing; this column represents a statistical ...
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... I V operating supply Automatic power-down SB1 current Note 25. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 Test Conditions V = Max mA, 333 MHz (× OUT 1/t MAX CYC (× 18) (× 36) 300 MHz (× ...
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... UNDER ZQ TEST RQ = 250 INCLUDING JIG AND (b) SCOPE /2), Undershoot: V > 1.5 V (Pulse width less than t CYC IL(AC) /I and load capacitance shown in ( CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Min Typ Max V + 0.2 – REF – – V REF Max = 1 1.5 V DDQ 165-ball FBGA Package 13.7 3.73 ALL INPUT PULSES 1 ...
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... When a part with a maximum frequency above 250 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated and outputs data with the output timings of that frequency range. 31. This part has a voltage regulator internally; t POWER Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 333 MHz Min Max [31] 1 – ...
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... For frequencies 300 MHz or below, the Cypress QDR II devices surpass the QDR consortium specification for PLL lock time (tKC lock µs (min. spec.) and will lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version. Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 333 MHz Min Max – ...
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... Outputs are disabled (high Z) one clock cycle after a NOP. 38. In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 Figure 6. Read/Write/Deselect Sequence t CYC ...
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... Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) Ordering Code 333 CY7C1425KV18-333BZC CY7C1412KV18-333BZC CY7C1414KV18-333BZC CY7C1414KV18-333BZXC CY7C1412KV18-333BZXI 300 CY7C1425KV18-300BZC CY7C1412KV18-300BZC CY7C1414KV18-300BZC CY7C1425KV18-300BZXC CY7C1412KV18-300BZXC CY7C1414KV18-300BZXC CY7C1414KV18-300BZI CY7C1412KV18-300BZXI ...
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... XXX 14XX K V18 Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 X Temperature Range Commercial = 0 C to +70 Industrial = –40 C to +85 Pb-free; X Absent = Leaded Package Type 165-ball FBGA Speed Grade: XXX = 333 MHz or 300 MHz or 250 MHz V18 = 1 ...
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... Package Diagram Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180 Document Number: 001-57825 Rev. *F CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 51-85180 *E Page ...
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... TAP test access port TCK test clock TMS test mode select TDI test data-in TDO test data-out Document Number: 001-57825 Rev. *F CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 Document Conventions Units of Measure Symbol Unit of Measure °C degree Celsius MHz megahertz µA microampere µs microsecond ...
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... Document History Page Document Title: CY7C1425KV18/CY7C1412KV18/CY7C1414KV18, 36-Mbit QDR Document Number: 001-57825 Orig. of Rev. ECN No. Change ** 2816620 VKN / AESA *A 2884865 VKN *B 3018546 NJY *C 3155124 VIDB *D 3165654 NJY *E 3436284 PRIT *F 3549927 PRIT Document Number: 001-57825 Rev. *F CY7C1412KV18, CY7C1414KV18 Submission Date 11/27/2009 New data sheet. ...
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... QDR registered trademark of Cypress Semiconductor Corporation. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB Revised March 13, 2012 CY7C1425KV18 CY7C1412KV18, CY7C1414KV18 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 ...