AS6C8016-55BINTR Alliance Memory, AS6C8016-55BINTR Datasheet - Page 5

• Manufacturer Part Number: AS6C8016-55BINTR
• Description: SRAM 8M, 2.7-5.5V, 55ns 512K x 16 Asyn SRAM
• Manufacturer: Alliance Memory

Specifications of AS6C8016-55BINTR

• Rohs: yes
• Factory Pack Quantity: 2000

TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
Notes :
1.WE#is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise t
4.t
5.At any given temperature and voltage condition, t
LB#,UB#
Address
Address
CLZ
Dout
Dout
CE#
OE#
NOVEMBER/2007, V 1.0
January 2007
NOVEMBER 2007
, t
BLZ,
t
OLZ
, t
Previous Data Valid
CHZ,
t
BHZ
and t
OHZ
High-Z
512K X 16 BIT SUPER LOW POWER CMOS SRAM
are specified with C
t
BLZ
t
CLZ
t
t
AA
AA
t
OLZ
t
ACE
t
BA
CHZ
t
t
Alliance Memory Inc.
RC
RC
t
OE
is less than t
L
= 5pF. Transition is measured ±500mV from steady state.
512K X 8 BIT LOW POWER CMOS SRAM
CLZ
, t
BHZ
Data Valid
.
is less than t
Data Valid
t
OH
t
t
BHZ
CHZ
t
OHZ
BLZ
t
OH
, t
OHZ
is less than t
AA
is the limiting parameter.
High-Z
OLZ.
Page 5 of 12
AS6C8016