70T3539MS166BC IDT, 70T3539MS166BC Datasheet
70T3539MS166BC
Specifications of 70T3539MS166BC
Related parts for 70T3539MS166BC
70T3539MS166BC Summary of contents
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... Interrupt and Collision Detection Flags ◆ Full synchronous operation on both ports – 6ns cycle time, 166MHz operation (12Gbps bandwidth) – Fast 3.6ns clock to data out – 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 166MHz Functional Block Diagram ...
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... The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70T3539M has been optimized for applications having unidirectional or bidirectional data flow Industrial and Commercial Temperature Ranges in bursts ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Pin Configuration (1,2,3,4) 10/07/ TDI NC A 17L I/O NC TDO A 18L 18L I/O I 18R 19L SS 16L I/O I/O PIPE/ FT I/O 20R 19R 20L I/O I/O I/O V 21R 21L 22L DDQL ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Pin Names Left Port Right Port Chip Enables (Input R/W R/W Read/Write Enable (Input Output Enable (Input Address (Input) 0L 18L 0R 18R I/O - I/O I/O - I/O Data Input/Output 0L 35L 0R 35R CLK ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Truth Table I—Read/Write and Enable Control CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ...
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... V Input Low Voltage -0.3 IL Input Low Voltage - (1) V -0.3 IL ZZ, OPT, PIPE/FT (min.) = -1.0V for pulse width less than t IL CYC (max 1.0V for pulse width less than t IH DDQ for that port must be set to V (2.5V), and V for that port must be supplied as indicated DD DDQX above ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Absolute Maximum Ratings Symbol Rating V V Terminal Voltage TERM with Respect to GND DD ( Terminal Voltage TERM DDQ (V ) with Respect to GND DDQ V (2) Input and I/O Terminal TERM (INPUTS and I/O's) Voltage with Respect to GND ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE I Dynamic Operating DD L Current (Both Outputs Disabled, Ports Active MAX CE I (6) Standby Current SB1 L (Both Ports - TTL MAX ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM AC Test Conditions (V Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT ∆ tCD (Typical, ns) - 3.3V/2.5V) DDQ GND to 3 0V/GND to 2.4V . GND to 3.0V/GND to 2.4V 2ns 1 ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol t Clock Cycle Time (Flow-Through) CYC1 (1) t Clock Cycle Time (Pipelined) CYC2 t Clock High Time (Flow-Through) CH1 t Clock Low Time (Flow-Through) ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Read Cycle for Pipelined Operation (1,2) (FT/PIPE = CYC2 t CH2 CLK (4) ADDRESS An (1 Latency) DATA OUT (1) OE Timing Waveform of Read Cycle for Flow-through Output ...
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... HA A ADDRESS 0 (B2) CE 0(B2 DATA OUT(B2) NOTES Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3539M for this waveform, and are setup for depth expansion in this example. ADDRESS OE, and ADS = V , R/W, CNTEN, and REPEAT = 1(B1) 1(B2 ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Left Port Write to Pipelined Right Port Read CLK "A" R/W "A " ADDRESS "A" MATCH DATA VALID IN"A" ( CLK "B" R/W "B" ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Pipelined Read-to-Write-to-Read ( CYC2 t t CH2 CLK (3) An ADDRESS DATA IN (1) DATA OUT READ NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK BEn (3) An ADDRESS DATA IN t CD1 (1) DATA OUT READ Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled) ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Pipelined Read with Address Counter Advance t CYC2 t t CH2 CLK ADDRESS t t SAD HAD ADS CNTEN ( DATA OUT READ EXTERNAL ADDRESS Timing Waveform of Flow-Through Read with Address Counter Advance ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs) t CYC2 t CH2 CLK ADDRESS (3) INTERNAL An ADDRESS t t SAD HAD ADS CNTEN DATA IN WRITE EXTERNAL ADDRESS Timing Waveform of Counter Repeat ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Waveform of Interrupt Timing CLK R ADDRESS (3) L 7FFFF ( INS INT R CLK R CE (1) R R/W R ADDRESS (3) R NOTES and All timing is the same for Left and Right ports. ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Waveform of Collision Timing CLK L t OFS ( ADDRESS L COL L CLK (4) ADDRESS COL R NOTES For reading port Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases. ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Timing Waveform - Entering Sleep Mode R/W Timing Waveform - Exiting Sleep Mode R/W OE DATA OUT (4) NOTES IH. 2. All timing is same for Left and Right ports has to be deactivated ( has to be deactivated (CE ...
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... Offering this function on chip also allows users to reduce their need for arbitration circuits, typically done in CPLD’s or FPGA’s. This reduces board space and design complexity, and gives the user more flexibility in developing a solution. Sleep Mode TThe IDT70T3539M is equipped with an optional sleep or low power = R per the R ...
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... JTAG signaling must be provided serially to each array and utilize the information provided in the Identification Register Definitions, Scan TDI TCK TMS TRST The IDT70T3539M can also be used in applications requiring expanded width, as indicated in Figure 4. Through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 72-bits or wider. IDT70T3539M ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM JTAG Timing Specifications t JF TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO. JTAG AC Electrical ...
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... Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com contacting your local IDT sales representative. Instruction Field ...
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... IDT70T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Ordering Information XXXXX A 999 A Device Power Speed Package Type Temperature IDT Clock Solution for IDT70T3539M Dual-Port Dual-Port I/O Specitications IDT Dual-Port Part Number Voltage I/O 70T3539M 3.3/2.5 LVTTL A Process/ Range Blank I BC 166 133 S 70T3539M Clock Specifications ...
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... Page 25 Removed "IDT" from orderable part number 02/04/10: Page 7 Corrected the Capacitance Table Title CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. and I in the DC Electrical Characteristics table 3 ZZ for SALES: ...