MAX6733UTWGD6-T Maxim Integrated, MAX6733UTWGD6-T Datasheet - Page 10

• Manufacturer Part Number: MAX6733UTWGD6-T
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX6730, MAX6731, MAX6732, MAX6733, MAX6734, MAX6735r

Specifications of MAX6733UTWGD6-T

• Number Of Voltages Monitored: 2
• Monitored Voltage: 0.9 V to 5 V
• Undervoltage Threshold: 1.62 V, 1.08 V
• Overvoltage Threshold: 1.71 V, 1.14 V
• Output Type: Active Low, Push-Pull
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 840 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23
• Chip Enable Signals: No
• Maximum Power Dissipation: 696 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 15 uA, 4 uA
• Supply Voltage - Min: 0.8 V

The RSTIN comparator derives power from V
the input voltage must remain less than or equal to
V
large-valued resistors, resulting in reduced power con-
sumption of the system.
The watchdog feature monitors µP activity through
the watchdog input (WDI). A rising or falling edge on
WDI within the watchdog timeout period (t
cates normal µP operation. WDO asserts low if WDI
remains high or low for longer than the watchdog
timeout period. Leaving WDI unconnected does not
disable the watchdog timer.
The MAX6730–MAX6735 include a dual-mode watch-
dog timer to monitor µP activity. The flexible timeout
architecture provides a long-period initial watchdog
mode, allowing complicated systems to complete
lengthy boots, and a short-period normal watchdog
mode, allowing the supervisor to provide quick alerts
when processor activity fails. After each reset event
(V
long initial watchdog period of 35s (min). The long
watchdog period mode provides an extended time for
the system to power up and fully initialize all µP and
system components before assuming responsibility for
routine watchdog updates.
Single-/Dual-/Triple-Voltage µP Supervisory
Circuits with Independent Watchdog Output
Figure 3. Watchdog Input/Output Timing Diagram (MR and WDO Not Connected)
10
CC
CC
RSTIN
V
V
WDO
CC
WDI
RST
CC
1. Low leakage current at RSTIN allows the use of
1,
______________________________________________________________________________________
2
power-up, brownout, or manual reset), there is a
(MIN)
V
CC
V
TH
t
RP
< t
WD-L
Watchdog
WD
CC
1, and
) indi-
< t
WD-S
The usual watchdog timeout period (1.12s min) begins
after the initial watchdog timeout period (t
or after the first transition on WDI (Figure 3). During nor-
mal operating mode, the supervisor asserts the WDO
output if the µP does not update the WDI with a valid
transition (high to low or low to high) within the standard
timeout period (t
Connect MR to WDO to force a system reset in the
event that no rising or falling edge is detected at WDI
within the watchdog timeout period. WDO asserts low
when no edge is detected by WDI, the RST output
asserts low, the watchdog counter immediately clears,
and WDO returns high. The watchdog counter restarts,
using the long watchdog period, when the reset timeout
period ends (Figure 4).
The MAX6730–MAX6735 guarantee proper operation
down to V
reset levels down to V
resistor from RST to GND. The resistor value used is not
critical, but it must be large enough not to load the
reset output when V
most applications, 100kΩ is adequate. Note that this
configuration does not work for the open-drain outputs
of MAX6730/MAX6732/MAX6734.
< t
WD-S
CC
= +0.8V. In applications that require valid
WD-S
t
WD-S
> t
WD-S
CC
) (1.12s min).
CC
Output Down to V
is above the reset threshold. For
Ensuring a Valid RESET
= 0V, use a 100kΩ pulldown
< t
WD-S
WD-L
< t
WD-S
CC
) expires
= 0V