M95128-RMN6TP STMicroelectronics, M95128-RMN6TP Datasheet
M95128-RMN6TP
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M95128-RMN6TP
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M95128-RMN6TP Summary of contents
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... Features ■ Compatible with SPI bus serial interface (positive clock SPI modes) ■ Single supply voltage: – 4.5 to 5.5 V for M95128 – 2.5 to 5.5 V for M95128-W – 1.8 to 5.5 V for M95128-R ■ High speed – 10 MHz clock rate write time ■ ...
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... CC Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Doc ID 5798 Rev 13 M95128, M95128-W, M95128-R ...
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... M95128, M95128-W, M95128-R 5.6 Write to Memory Array (WRITE 5.6.1 6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . 22 ...
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... AC measurement conditions Table 11. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 12. DC characteristics (M95128, device grade 3 Table 13. DC characteristics (M95128-W, device grade Table 14. DC characteristics (M95128-W, device grade Table 15. DC characteristics (M95128- Table 16. AC characteristics (M95128, device grade Table 17. AC characteristics (M95128-W, device grade Table 18. AC characteristics (M95128-W, device grade Table 19 ...
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... M95128, M95128-W, M95128-R List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO, UFDFPN and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 9 ...
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... Description 1 Description The M95128, M95128-W and M95128-R are electrically erasable programmable memory (EEPROM) devices accessed by a high speed SPI-compatible bus. The memory array is organized as 16384 × 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in The device is selected when Chip Select (S) is taken low ...
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... M95128, M95128-W, M95128-R Table 1. Signal names Signal name HOLD Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground Doc ID 5798 Rev 13 Description Direction Input Input Output Input Input Input 7/44 ...
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... Memory organization The memory is organized as shown in Figure 3. Block diagram HOLD W Control Logic Address Register and Counter 8/44 M95128, M95128-W, M95128-R Figure 3. High Voltage Generator I/O Shift Register Data Register 1 Page X Decoder Doc ID 5798 Rev 13 Status Register Size of the Read only EEPROM ...
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... M95128, M95128-W, M95128-R 3 Signal description See Figure 1: Logic diagram connected to this device. 3.1 Serial Data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 3.2 Serial Data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written ...
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... Table 9. 10/44 supply voltage (min), V (max)] range must be applied (see CC CC (min), V (max)] range defined Doc ID 5798 Rev 13 M95128, M95128-W, M95128-R voltage CC Table 7, Table 8 line with CC /V package CC SS reaches a valid and stable V CC Table 7, Table 8 and and ) ...
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... M95128, M95128-W, M95128-R 3.8.3 Power-up conditions When the power supply is turned on, V time, the Chip Select (S) line is not allowed to float but should follow the V therefore recommended to connect the S line to V Figure 12). In addition, the Chip Select (S) input offers a built-in safety feature edge-sensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S) ...
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... Serial Clock (C) already being low. Figure 4 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. Figure 4. Hold condition activation C HOLD 12/44 M95128, M95128-W, M95128-R Figure 4). Hold Condition Doc ID 5798 Rev 13 Hold Condition AI02029D ...
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... SPI bus. Table 2. Write-protected block size Status Register bits BP1 (RDSR). Protected block BP0 0 none 1 Upper quarter 0 Upper half 1 Whole memory Doc ID 5798 Rev 13 Operating features Array addresses protected M95128, M95128-W, M95128-R none 3000h - 3FFFh 2000h - 3FFFh 0000h - 3FFFh 13/44 ...
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... Write to Memory Array 5, to send this instruction to the device, Chip Select (S) is driven low Instruction D High Impedance Q Doc ID 5798 Rev 13 M95128, M95128-W, M95128-R Table 3. Table 3), the device automatically Instruction format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 5 6 ...
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... M95128, M95128-W, M95128-R 5.2 Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high ...
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... Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4. Status Register format b7 SRWD Status Register Write Protect 16/44 Table 4) becomes protected against Write Doc ID 5798 Rev 13 M95128, M95128-W, M95128-R Figure 7. BP1 BP0 WEL Block Protect bits Write Enable Latch bit Write In Progress bit b0 WIP ...
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... M95128, M95128-W, M95128-R Figure 7. Read Status Register (RDSR) sequence High Impedance Instruction Status Register Out MSB Doc ID 5798 Rev 13 Instructions Status Register Out MSB 7 AI02031E 17/44 ...
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... The values in the BP1 and BP0 bits can be changed Status Register is Hardware Hardware write protected Protected The values in the BP1 (HPM) and BP0 bits cannot be changed Doc ID 5798 Rev 13 M95128, M95128-W, M95128-R Table 16, Table 17, Figure 8. Memory content (1) Protected area Unprotected area Ready to accept Write ...
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... M95128, M95128-W, M95128-R The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of whether Write Protect (W) is driven high or low ...
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... High Impedance Q 1. The most significant address bits (b15, b14) are Don’t Care. 20/ send this instruction to the device, Chip Select (S) is first driven low Instruction 16-Bit Address MSB Doc ID 5798 Rev 13 M95128, M95128-W, M95128 Data Out MSB Data Out 2 7 AI01793D ...
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... M95128, M95128-W, M95128-R 5.6 Write to Memory Array (WRITE) As shown in Figure low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. The self-timed write cycle, triggered by the rising edge of Chip Select (S), continues for a period t of which the Write in Progress (WIP) bit is reset to 0 ...
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... The most significant address bits (b15, b14) are Don’t Care. 5.6.1 ECC (error correction code) and write cycling Most M95128, M95128-W and M95128-R devices offer an ECC (error correction code) logic which compares each 4-byte word with 6 EEPROM bits of ECC (the list of concerned devices is defined in temperature grade)) ...
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... M95128, M95128-W, M95128-R 6 Delivery state The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized Connecting to the SPI bus These devices are fully compatible with the SPI protocol. ...
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... C remains at 0 for (CPOL=0, CPHA=0) ● C remains at 1 for (CPOL=1, CPHA=1) Figure 13. SPI modes supported CPOL CPHA 24/44 requirement is met. The typical value 100 k. SHCH Figure MSB Doc ID 5798 Rev 13 M95128, M95128-W, M95128-R 13, is the clock polarity when the MSB AI01438B ...
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... M95128, M95128-W, M95128-R 8 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... T A Ambient operating temperature (device grade 3) Table 9. Operating conditions (M95128-R) Symbol V Supply voltage CC T Ambient operating temperature A 26/44 Parameter Parameter Parameter Doc ID 5798 Rev 13 M95128, M95128-W, M95128-R Min. Max. Unit 4.5 5.5 V –40 125 °C Min. Max. Unit 2.5 5.5 V –40 85 ° ...
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... Figure 14. AC measurement I/O waveform Table 11. Capacitance Symbol C Output capacitance (Q) OUT Input capacitance ( Input capacitance (other pins) 1. Sampled only, not 100% tested Table 12. DC characteristics (M95128, device grade 3) Symbol I Input leakage current LI I Output leakage current LO I Supply current CC Supply current I ...
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... DC and AC parameters 2. Characterized only, not 100% tested. Table 13. DC characteristics (M95128-W, device grade 6) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current (Read) CC (1) I Supply current (Write) CC0 Supply current I CC1 (Standby Power mode) V Input low voltage IL V Input high voltage ...
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... Output low voltage OL V Output high voltage OH Internal reset (2) V RES threshold voltage 1. If the application uses the M95128-R device with 2.5 V < V refer to Table 17: AC characteristics (M95128-W, device grade 6) 2. Characterized only, not 100% tested. Test condition V = 2.5 V and I = –0 ...
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... DC and AC parameters Table 16. AC characteristics (M95128, device grade 3) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH t HLCH t CLHL t CLHH ( SHQZ DIS t t CLQV CLQX HO (2) ...
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... M95128, M95128-W, M95128-R Table 17. AC characteristics (M95128-W, device grade 6) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH t HLCH t CLHL t CLHH ( SHQZ DIS t t CLQV CLQX ...
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... DC and AC parameters Table 18. AC characteristics (M95128-W, device grade 3) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH t HLCH t CLHL t CLHH ( SHQZ DIS t t CLQV CLQX HO (2) ...
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... HHQV LZ ( HLQZ the application uses the M95128-R at 2.5 V V Table 17 instead of the above table. 2. This is preliminary data must never be less than the shortest possible clock period Value guaranteed by characterization, not 100% tested in production. Test conditions specified in Table 10 Parameter Clock frequency ...
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... DC and AC parameters Figure 15. Serial input timing S tCHSL C tDVCH D Q Figure 16. Hold timing HOLD 34/44 tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 5798 Rev 13 M95128, M95128-W, M95128-R tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV AI01448c AI01447d ...
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... M95128, M95128-W, M95128-R Figure 17. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN tCH tCHCL tCL tQLQH tQHQL Doc ID 5798 Rev 13 DC and AC parameters tSHSL tSHQZ AI01449f 35/44 ...
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... Doc ID 5798 Rev 13 M95128, M95128-W, M95128 45˚ c 0.25 mm GAUGE PLANE SO-A (1) inches Typ Min 0.0039 0.0492 0.011 0.0067 0.1929 0.189 0.2362 ...
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... M95128, M95128-W, M95128-R Figure 19. TSSOP8 – 8-lead thin shrink small outline, package outline Drawing is not to scale. Table 21. TSSOP8 – 8-lead thin shrink small outline, package mechanical data Symbol N (number of leads) 1. Values in inches are converted from mm and rounded to 4 decimal digits. ...
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... Doc ID 5798 Rev 13 M95128, M95128-W, M95128 UFDFPN- (1) inches Typ Min Max 0.0217 0.0177 0.0236 0.0008 0 0.002 0.0098 0.0079 0.0118 0.0787 0.0748 ...
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... M95128, M95128-W, M95128-R 11 Part numbering Table 23. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM Device function 128 = 128 Kbit (16384 x 8) Operating voltage blank = V = 4 2 1 Package MN = SO8 (150 mils width TSSOP8 (169 mils width UFDFPN8 (MLP8 2 × ...
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... Part numbering Table 24. Available M95128x products (package, voltage range, temperature grade) Package SO8N (MN) UFDFPN8 (MLP8) 2 × (MB) TSSOP (DW) 1. Grade 3 products (without ECC) are codified as /P and /PC in 40/44 M95128-R M95128-W (1 5 5.5 V) Grade 6 Grade 6 Grade 3 Grade 6 - Grade 6 Grade 3 Table 23: Ordering information ...
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... Document promoted from Preliminary Data to Full Data Sheet Announcement made of planned upgrade to 10 MHz clock for the 5V, –40 2.7 to 85°C, range. M95128 split off to its own datasheet. Data added for new and forthcoming 2.8 products, including availability of the SO8 narrow package. 2.9 Omission of SO8 narrow package mechanical data remedied 2 ...
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... Table 19: AC characteristics T added to Table 6: Absolute maximum A PDIP8 (BN) and SO8 wide (MW) packages removed. M95128-W and M95128-R are no longer under development. Test conditions changed for V characteristics (M95128-W, device grade Figure 12: Bus master and memory devices on the SPI bus SO8N package specifications updated (see ...
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... Table 25. Document revision history (continued) Date Revision 11-Jul-2008 17-Feb-2009 12-Jan-2010 02-Mar-2010 M95128, device grade 3 devices is now offered at 10 MHz frequency. Section 3.8: Supply voltage (V Status Register (WRSR) on page 18 Table 15: DC characteristics (M95128-R) on page 29 t and t modified in Table 16: AC characteristics (M95128, device ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 44/44 Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 5798 Rev 13 M95128, M95128-W, M95128-R ...