M95256-WMN6TP STMicroelectronics, M95256-WMN6TP Datasheet - Page 24
![IC EEPROM 256KBIT 5MHZ 8SOIC](/photos/1/38/13851/497-8-soic_sml.jpg)
M95256-WMN6TP
Manufacturer Part Number
M95256-WMN6TP
Description
IC EEPROM 256KBIT 5MHZ 8SOIC
Manufacturer
STMicroelectronics
Specifications of M95256-WMN6TP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
256K (32K x 8)
Speed
5MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Organization
32 K x 8
Interface Type
SPI
Maximum Clock Frequency
5 MHz
Access Time
60 ns
Supply Voltage (max)
6.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
5 mA
Maximum Operating Temperature
+ 130 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2.5 V, 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8691-2
M95256-WMN6TP
M95256-WMN6TP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M95256-WMN6TP
Manufacturer:
STMicroelectronics
Quantity:
70 032
Part Number:
M95256-WMN6TP
Manufacturer:
ST
Quantity:
20 000
Instructions
5.9
Figure 15. Read Lock Status sequence
5.10
24/47
Read Lock Status (available only in M95256-DR devices)
The Read Lock Status instruction (see
locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip
Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted
in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care.
The Lock bit is the LSB (least significant bit) of the byte read on Serial Data output (Q). It is
at ‘1’ when the lock is active and at ‘0’ when the lock is not active. If Chip Select (S)
continues to be driven low, the same data byte is shifted out. The read cycle is terminated by
driving Chip Select (S) high.
The instruction sequence is shown in
Lock ID (available only in M95256-DR devices)
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the
instruction code, the address and a data byte on Serial Data input (D), and driving Chip
Select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't
Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write
cycle whose duration is t
Figure
16.
W
(specified in
Doc ID 12276 Rev 13
Figure
Table
Table
15.
4) allows to check if the Identification Page is
20). The instruction sequence is shown in
M95256-DR, M95256, M95256-W, M95256-R