W971GG6JB-25 Winbond Electronics, W971GG6JB-25 Datasheet - Page 11
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W971GG6JB-25
Manufacturer Part Number
W971GG6JB-25
Description
IC DDR2-800 SDRAM 1GB 84-WBGA
Manufacturer
Winbond Electronics
Datasheet
1.W971GG6JB-25.pdf
(87 pages)
Specifications of W971GG6JB-25
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (64M x 16)
Speed
2.5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
84-WBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q5804012
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
W971GG6JB-25
Manufacturer:
Winbond
Quantity:
9 560
Part Number:
W971GG6JB-25
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Company:
Part Number:
W971GG6JB-25I
Manufacturer:
SIEMENS
Quantity:
24
SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2
does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must
be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the
table for specific codes.
Note:
1. WR (write recovery for Auto-precharge) min is determined by tCK(avg) max and WR max is determined by tCK(avg) min.
7.2.2
7.2.2.1
( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L, BA2 = "L" A0 to A12 =
Register data)
The extended mode register (1) stores the data for enabling or disabling the DLL, output driver
strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended
mode register (1) is not defined, therefore the extended mode register (1) must be programmed during
initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register (1). The mode register set command
cycle time (t
Extended mode register (1) contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. A0 is used for
DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the
additive latency, A[9:7] are used for OCD control, A10 is used for DQS disable. A2 and A6 are used
for ODT setting.
BA1
WR[cycles] = RU{ tWR[nS] / tCK(avg)[nS] }, where RU stands for round up. The mode register must be programmed to this
value. This is also used with tRP to determine tDAL.
0
0
1
1
BA0
0
1
0
1
Extend Mode Register Set Commands (EMRS)
A12
0
1
Extend Mode Register Set Command (1), EMR (1)
BA2
0
MRD
A8
0
1
MRS mode
EMR (1)
EMR (2)
EMR (3)
Active power down exit time
BA1
MR
Slow exit (use tXARDS)
0
) must be satisfied to complete the write operation to the extended mode register (1).
Fast exit (use tXARD)
DLL Reset
Yes
No
BA0
0
A12
PD
A11
Figure 2 – Mode Register Set (MRS)
A10
WR
Write recovery for Auto-precharge
A11
0
0
0
0
1
1
1
1
A9
A10
0
0
1
1
0
0
1
1
DLL
A8
A7
0
1
A9
0
1
0
1
0
1
0
1
TM
A7
Normal
Mode
Test
- 11 -
Reserved
WR *
A6
2
3
4
5
6
7
8
CAS Latency
A5
A4
Publication Release Date: Mar. 28, 2011
A3
A3
BT
0
1
A2
Burst Length
Burst Type
Sequential
Interleave
A6
0
0
0
0
1
1
1
1
A1
CAS Latency
A5
0
0
1
1
0
0
1
1
W971GG6JB
A0
A4
0
1
0
1
0
1
0
1
A2
0
0
Burst Length
Address Field
Mode Register
Reserved
Reserved
Reserved
Latency
A1
1
1
3
4
5
6
7
Revision A07
A0
0
1
BL
4
8