CY7C1356C-166AXC Cypress Semiconductor Corp, CY7C1356C-166AXC Datasheet

Page 1

... SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354C and CY7C1356C are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle ...

Page 2

... Logic Block Diagram – CY7C1356C (512 K × 18) A0, A1, A MODE CLK C CEN WRITE ADDRESS ADV/ CE1 CE2 CE3 ZZ Document Number: 38-05538 Rev. *L ADDRESS REGISTER BURST A0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 1 REGISTER 2 WRITE REGISTRY AND DATA COHERENCY WRITE CONTROL LOGIC DRIVERS ...

Page 3

... TAP AC Switching Characteristics ............................... 14 3.3 V TAP AC Test Conditions ....................................... 15 3.3 V TAP AC Output Load Equivalent ......................... 15 2.5 V TAP AC Test Conditions ....................................... 15 2.5 V TAP AC Output Load Equivalent ......................... 15 Document Number: 38-05538 Rev. *L CY7C1354C, CY7C1356C TAP DC Electrical Characteristics and Operating Conditions ............................................. 15 Identification Register Definitions ................................ 15 Scan Register Sizes ....................................................... 16 Identification Codes ....................................................... 16 Boundary Scan Exit Order (256 K × ...

Page 4

... DQa 18 63 DQa DQb DDQ 20 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1354C, CY7C1356C 166 MHz Unit 3.5 ns 180 DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa DQa 63 DQa DDQ DQa ...

Page 5

... Document Number: 38-05538 Rev. *L Figure 2. 119-ball BGA Pinout CY7C1354C (256 K × 36 NC/18M ADV/ DQP CLK CEN DQP MODE NC/72M TMS TDI TCK TDO CY7C1356C (512 NC/18M ADV/ CLK CEN DQP MODE NC/36M A TMS TDI TCK TDO CY7C1354C, CY7C1356C DDQ CE NC ...

Page 6

... DDQ N DQP DDQ P NC/144M NC/72M A R MODE NC/36M A Document Number: 38-05538 Rev. *L Figure 3. 165-ball FBGA CY7C1354C (256 K × 36 CEN CLK TDI A1 TDO A A0 TCK TMS CY7C1356C (512 K × 18 CEN CLK TDI A1 TDO TCK TMS CY7C1354C, CY7C1356C ADV/ NC/18M DQP V SS DDQ ...

Page 7

... BW controls DQ and DQP select/deselect the device. 3 and CE to select/deselect the device select/deselect the device. 2 –DQ are placed in a tristate condition. The outputs are controlled DQP controlled CY7C1354C, CY7C1356C and DQP , BW controls DQ and DQP During [a:d]. is controlled DQP is controlled Page [+] Feedback ...

Page 8

... On the next clock rise the data presented to DQ (DQ /DQP a,b,c,d CY7C1356C or a subset for byte write operations, see the table Partial Write Cycle Description on page 10 latched into the device and the write is complete. CY7C1354C, CY7C1356C Single Read – ...

Page 9

... The output enable (OE) can be deasserted HIGH before presenting data to (DQ /DQP for CY7C1354C and DQ a,b,c,d a,b,c,d CY7C1356C) inputs. Doing so will tristate the output drivers safety precaution, DQ (DQ and DQP CY7C1354C and DQ /DQP for a,b a,b automatically tristated during the data portion of a write cycle, regardless of the state of OE ...

Page 10

... Truth Table The Truth Table for CY7C1354C and CY7C1356C follows. Operation Deselect cycle Continue deselect cycle Read cycle (begin burst) Read cycle (continue burst) NOP/dummy read (begin burst) Dummy read (continue burst) Write cycle (begin burst) Write cycle (continue burst) NOP/WRITE ABORT (begin burst) ...

Page 11

... Partial Write Cycle Description The following table lists the Partial Write Cycle Description for CY7C1356C. Function (CY7C1356C) Read Write – no bytes written Write byte a − (DQ and DQP a a) Write byte b – (DQ and DQP b b) Write both bytes Notes 10 “Don't Care” Logic HIGH Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one bytewrite select is active, BWx = valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details ...

Page 12

... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1354C/CY7C1356C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These ...

Page 13

... Capture-DR state, an input or output undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. CY7C1354C, CY7C1356C INTEST or the PRELOAD ...

Page 14

... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions TDIS t TDIH t TDOV t TDOX DON’ UNDEFINED Description / ns CY7C1354C, CY7C1356C 5 6 Min Max Unit 50 – ns – 20 MHz 20 – – ns – – – ...

Page 15

... DDQ V = 2.5 V DDQ V = 3.3 V DDQ V = 2.5 V DDQ GND < V < DDQ CY7C1354C CY7C1356C 000 000 01011001000010110 Reserved for future use. 00000110100 00000110100 1 1 CY7C1354C, CY7C1356C to 2 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.4 – V 2.0 – V 2.9 – V 2.1 – V – ...

Page 16

... Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 38-05538 Rev. *L CY7C1354C, CY7C1356C Bit Size (× 36) Bit Size (× 18 ...

Page 17

... J10 20 L6 K10 21 N6 L10 22 P7 M10 23 N7 J11 24 M6 K11 25 L7 L11 26 K6 M11 27 P6 N11 28 T4 R11 29 A3 R10 30 C5 P10 Document Number: 38-05538 Rev. *L Bit # 119-ball ID 165-ball Not Bonded Not Bonded (Preset to 1) (Preset CY7C1354C, CY7C1356C Page [+] Feedback ...

Page 18

... Not Bonded (Preset to 0) Not Bonded (Preset Not Bonded (Preset to 0) Not Bonded (Preset Not Bonded (Preset to 0) Not Bonded (Preset R11 64 B2 R10 65 Not Bonded (Preset to 0) Not Bonded (Preset to 0) P10 Not Bonded (Preset CY7C1354C, CY7C1356C 165-ball Not Bonded (Preset Page [+] Feedback ...

Page 19

... SS DD ≤ V output disabled I DDQ, /2), undershoot: V (AC) > –2 V (Pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1354C, CY7C1356C Description Test Condi- Typ Max* Unit tions Logical 25 °C 320 368 single-bit upsets Logical 25 °C 0 0.01 multi-bit upsets Single event 85 ° ...

Page 20

... MHz 3 2 DDQ 5 5 100 TQFP Test Conditions Max Test conditions follow standard 29.41 test methods and procedures for measuring thermal 6.13 impedance, per EIA/JESD51. CY7C1354C, CY7C1356C Min Max Unit – 250 mA – 220 mA – 180 mA – 130 mA – 120 mA – ...

Page 21

... Figure 4. AC Test Loads and Waveforms R = 317 Ω 3 DDQ GND 351 Ω INCLUDING JIG AND SCOPE ( 1667 Ω 2 DDQ GND 1538 Ω INCLUDING JIG AND (b) SCOPE CY7C1354C, CY7C1356C ALL INPUT PULSES 90% 90% 10% 10% ≤ ≤ (c) ALL INPUT PULSES 90% 90% 10% 10% ≤ ≤ (c) Page [+] Feedback ...

Page 22

... V minimum initially, before a Read or Write operation can be DD and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1354C, CY7C1356C –200 –166 Unit Min Max Min Max 1 – ...

Page 23

... DOH CLZ D(A1) D(A2) D(A2+1) Q(A3) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1354C, CY7C1356C OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) ...

Page 24

... The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. Document Number: 38-05538 Rev. *L [31, 32, 33 D(A1) Q(A2) Q(A3) READ WRITE STALL NOP Q(A3) D(A4) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH LOW CY7C1354C, CY7C1356C CHZ D(A4) Q(A5) READ DESELECT CONTINUE Q(A5) DESELECT is HIGH. 3 Page [+] Feedback ...

Page 25

... Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 35. I/Os are in high Z when exiting ZZ sleep mode. Document Number: 38-05538 Rev. *L [34, 35] Figure 7. ZZ Mode Timing DDZZ High-Z DON’T CARE CY7C1354C, CY7C1356C t ZZREC t RZZI DESELECT or READ Only Page [+] Feedback ...

Page 26

... Package (MHz) Ordering Code Diagram 166 CY7C1354C-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free CY7C1356C-166AXC CY7C1354C-166BGC 51-85115 119-ball Ball Grid Array (14 × 22 × 2.4 mm) CY7C1356C-166BGC CY7C1354C-166AXI 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free CY7C1356C-166AXI 200 CY7C1354C-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 × ...

Page 27

... Package Diagrams Figure 8. 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm), 51-85050 Document Number: 38-05538 Rev. *L CY7C1354C, CY7C1356C 51-85050 *D Page [+] Feedback ...

Page 28

... Figure 9. 119-ball BGA (14 × 22 × 2.4 mm), 51-85115 Document Number: 38-05538 Rev. *L CY7C1354C, CY7C1356C 51-85115 *C Page [+] Feedback ...

Page 29

... Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm), 51-85180 Document Number: 38-05538 Rev. *L CY7C1354C, CY7C1356C 51-85180 *C Page [+] Feedback ...

Page 30

... TDI test data input TMS test mode select TDO test data output TQFP thin quad flat pack WE write enable Document Number: 38-05538 Rev. *L CY7C1354C, CY7C1356C Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes ...

Page 31

... Document History Page Document Title: CY7C1354C/CY7C1356C 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05538 Submission Revision ECN Date ** 242032 See ECN *A 278130 See ECN *B 284431 See ECN *C 320834 See ECN *D 351895 See ECN *E 377095 See ECN ...

Page 32

... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05538 Rev Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised March 30, 2011 CY7C1354C, CY7C1356C PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...