CY7C1356C-166AXC Cypress Semiconductor Corp, CY7C1356C-166AXC Datasheet - Page 8

• Manufacturer Part Number: CY7C1356C-166AXC
• Description: IC SRAM 9MBIT 166MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1356C-166AXC

• Memory Size: 9M (512K x 18)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3.5 ns
• Maximum Clock Frequency: 166 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2122; CY7C1356C-166AXC

Pin Definitions
Functional Overview
The CY7C1354C and CY7C1356C are synchronous-pipelined
burst NoBL SRAMs designed specifically to eliminate wait states
during write/read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the clock.
The clock signal is qualified with the clock enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and all
internal states are maintained. All synchronous operations are
qualified with CEN. All data outputs pass through output registers
controlled by the rising edge of the clock. Maximum access delay
from the clock rise (t
Accesses can be initiated by asserting all three chip enables
(CE
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and enables the requested data to propagate to the
input of the output register. At the rising edge of the next clock
the requested data is allowed to propagate through the output
register and to the data bus within 2.8 ns (250 MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW for the device to drive out
the requested data. During the second clock, a subsequent
Document Number: 38-05538 Rev. *L
V
V
NC
NC (18, 36,
72, 144, 288,
576, 1G)
ZZ
DDQ
SS
Pin Name
1
, CE
3
are all asserted active, (3) the write enable input signal
2
, CE
I/O power supply Power supply for the I/O circuitry.
3
) active at the rising edge of the clock. If clock
asynchronous
I/O Type
Ground
Input-
CO
(continued)
–
–
) is 2.8 ns (250 MHz device).
[d:a]
can be used to conduct byte write
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
288M, 576M, and 1G densities.
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep”
condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
1
, CE
2
, CE
3
) and an
1
, CE
2
,
operation (read/write/deselect) can be initiated. Deselecting the
device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output tristates following the next clock rise.
Burst Read Accesses
The CY7C1354C and CY7C1356C have an on-chip burst
counter that enables the user the ability to supply a single
address and conduct up to four reads without reasserting the
address inputs. ADV/LD must be driven LOW to load a new
address into the SRAM, as described in the
Accesses
mined by the MODE input signal. A LOW input on MODE selects
a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wrap around when incremented sufficiently. A
HIGH input on ADV/LD increments the internal burst counter
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
asserted LOW. The address presented to A
the address register. The write signals are latched into the
control logic block.
On the subsequent clock rise the data lines are automatically
tristated regardless of the state of the OE input signal. This
enables the external logic to present the data on DQ
(DQ
CY7C1356C). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
if the appropriate control signals are asserted.
On the next clock rise the data presented to DQ
(DQ
CY7C1356C or a subset for byte write operations, see the table
Partial Write Cycle Description on page 10
latched into the device and the write is complete.
Pin Description
a,b,c,d
a,b,c,d
3
are all asserted active, and (3) the write signal WE is
/DQP
/DQP
section. The sequence of the burst counter is deter-
a,b,c,d
a,b,c,d
CY7C1354C, CY7C1356C
for CY7C1354C and DQ
for CY7C1354C and DQ
0
for details) inputs is
–A
16
a,b
a,b
is loaded into
Single Read
Page 8 of 32
/DQP
/DQP
and DQP
and DQP
1
a,b
a,b
, CE
for
for
2
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