MAX6841IUKD4+T Maxim Integrated, MAX6841IUKD4+T Datasheet - Page 18

• Manufacturer Part Number: MAX6841IUKD4+T
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX6841, MAX6842, MAX6843, MAX6844, MAX6845r

Specifications of MAX6841IUKD4+T

• Number Of Voltages Monitored: 1
• Monitored Voltage: 0.9 V to 1.5 V
• Undervoltage Threshold: 1.35 V
• Overvoltage Threshold: 1.425 V
• Output Type: Active High, Active Low, Push-Pull
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 2240 ms
• Supply Voltage - Max: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23
• Chip Enable Signals: No
• Maximum Power Dissipation: 571 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 8.1 uA
• Supply Voltage - Min: 0.75 V

set for Intel VRM 9.0/9.1 and AMD Athlon. The
MAX1939 is set for AMD Athlon Mobile.
The MAX1937/MAX1938/MAX1939 allow the VID_ code
to be changed while the converter is operating (on-the-
fly). The slew rate at which the output voltage is chang-
ing is controlled through TIME. The slew rate is
adjusted externally by connecting a 47kΩ to 470kΩ
resistor (R
select the R
where SR is the slew rate of the output voltage in V/µs.
The output voltage is stepped up or down in 25mV
steps until it reaches the voltage set by the new VID
code.
PWRGD is an open-drain output that is pulled low when
the output voltage deviates more than 12.5% from its
regulation voltage (set by VID_ inputs). PWRGD is
pulled low in shutdown, input UVLO, and during start-
up. Any fault condition forces PWRGD low until the fault
is cleared, and the IC is reset by cycling power at V
or momentarily toggling EN. For logic-level output volt-
ages, connect an external pullup resistor between
PWRGD and the logic power supply. A 100kΩ resistor
works well in most applications.
Two-Phase Desktop CPU Core Supply
Controllers with Controlled VID Change
Figure 4. Transient Response Regions
18
______________________________________________________________________________________
I
V
LOAD
OUT
(dV/dt = I
CAPACITIVE SAG
TIME
TIME
OUT
/C
) from TIME to GND. To set the slew rate,
OUT
VID_ Change Slew Rate (TIME)
resistor using the following equation:
)
Power-Good Output (PWRGD)
ESR VOLTAGE STEP
R
(I
TIME
STEP
x R
ESR
=
)
521
SR
RECOVERY
( )
(dV/dt = I
CAPACITIVE SOAR
Ω
OUT
/C
OUT
)
DD
For most applications, an inductor value of 0.5µH to
1µH is recommended. The inductance is set by the
desired amount of inductor current ripple (LIR). A larger
inductance value minimizes output ripple current and
increases efficiency, but slows transient response. For
the best compromise of size, cost, and efficiency, a LIR
of 30% to 40% is recommended (LIR = 0.3 to 0.4). The
inductor value is found from:
where f
The selected inductor should have the lowest possible
equivalent DC resistance and a saturation current
greater than the peak inductor current (I
found from:
The output capacitor must have low enough ESR to
meet output ripple and load-transient requirements.
Also, the capacitance value must be high enough to
absorb the inductor energy going from a full-load to a
no-load condition without tripping the OVP circuit.
In CPU core power supplies and other applications
where the output is subject to large load transients, the
output capacitor’s size typically depends on how much
ESR is needed to prevent the output from dipping too
low under a load transient. Ignoring the sag due to
finite capacitance:
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of OS-
CONs, SP capacitors, POSCAPs, and other electrolytic
capacitors). Generally, ceramic capacitors are not rec-
ommended for bulk output capacitance but make
excellent high-frequency decoupling capacitors.
Once enough capacitance is added to meet the over-
shoot requirement, undershoot at the rising load edge
sw
is the actual switching frequency of a phase.
R
L
I
PEAK
ESR
=
V
IN
= V
=
×
V
I
OUT
LOAD MAX
f
STEP(MAX)
Output Capacitor Selection
SW
Output Inductor Selection
×
×
(
I
LOAD MAX
(
V
Design Procedure
IN
)
−
/ ΔI
×
(
V
⎛
⎜
⎝
OUT
1
LOAD(MAX)
+
)
LIR
×
)
2
LIR
⎞
⎟
⎠
PEAK
). I
PEAK
is