MAX6841IUKD4+T Maxim Integrated, MAX6841IUKD4+T Datasheet - Page 20

• Manufacturer Part Number: MAX6841IUKD4+T
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX6841, MAX6842, MAX6843, MAX6844, MAX6845r

Specifications of MAX6841IUKD4+T

• Number Of Voltages Monitored: 1
• Monitored Voltage: 0.9 V to 1.5 V
• Undervoltage Threshold: 1.35 V
• Overvoltage Threshold: 1.425 V
• Output Type: Active High, Active Low, Push-Pull
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 2240 ms
• Supply Voltage - Max: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23
• Chip Enable Signals: No
• Maximum Power Dissipation: 571 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 8.1 uA
• Supply Voltage - Min: 0.75 V

V
resistor-divider from REF to GND. Select resistors R3
and R4 such that the current through the divider is at
least 5µA:
A typical value for R3 is 200kΩ; then solve for R4 using:
Voltage positioning dynamically changes the output-
voltage set point in response to the load current. When
the output is loaded, the signals fed back from the cur-
rent-sense inputs adjust the output voltage set point,
thereby decreasing power dissipation. The load-tran-
sient response of this control loop is extremely fast yet
well controlled, so the amount of voltage change can
be accurately confined within the limits stipulated in the
microprocessor power-supply guidelines. To under-
stand the benefits of dynamically adjusting the output
voltage, see the Voltage Positioning (VPOS) section.
The amount of output voltage change is adjusted by an
external gain resistor (R
REF and VPOS. The output voltage changes in response
to the load current as follows:
where V
the VID code (Table 1), and the voltage-positioning
transconductance (g
the value of the current-sense resistor connected from
CS_ to PGND. If the on-resistance of the low-side
MOSFETs is used instead of current-sense resistors for
current sensing, then use the maximum on-resistance
of the low-side MOSFETs for R
above.
Power dissipation in the high-side MOSFET is worst at
high duty cycles (maximum output voltage, minimum
input voltage). Two major factors contribute to the high-
side power dissipation, conduction losses, and switch-
ing losses. Conduction losses are because of current
flowing through a resistance, and can be calculated
from:
Two-Phase Desktop CPU Core Supply
Controllers with Controlled VID Change
20
ILIM
V
OUT
______________________________________________________________________________________
is set from 0.5V to 2V by connecting ILIM to a
VID
=
V
VID
is the programmed output voltage set by
Setting the Voltage Positioning
−
g
R
m VPOS
R
4
(
MOSFET Power Dissipation
3
m(VPOS)
=
+
R
VPOS
3
R
)
×
4 400
×
2
≤
R
). Connect R
) is typically 20µS. R
V
−
VPOS
ILIM
V
ILIM
k
Ω
CS
×
⎛
⎜
⎝
I
in the equation
OUT
VPOS
2
×
R
CS
between
⎞
⎟
⎠
CS
is
where R
MOSFET and V
duction losses, select a MOSFET with a low R
Switching losses are also a major contributor to power
dissipation in the high-side MOSFET. Switching losses
are difficult to precisely calculate and should be mea-
sured in the circuit. To estimate the switching losses,
use the following equation:
where I
valley inductor currents, t
rise times of the high-side MOSFET, and f
switching frequency (about 250kHz).
The total power dissipated in the high-side MOSFET is
then found from:
The power dissipation in the low-side MOSFET is high-
est at low duty cycles (high input voltage, low output
voltage), and is mainly because of conduction losses:
Switching losses in the low-side MOSFET are small
because of its voltage being clamped by the body
diode. Switching losses can be estimated from:
where I
current, t
conducts through its body diode, and V
ward voltage drop across the body diode.
The total power dissipation in the low-side MOSFET is:
During normal operation, power dissipation in the con-
troller is mostly from the gate drivers. This can be cal-
culated from the following equation:
P
P
D HS SW
D LS COND
P
(
(
D HS COND
P
PEAK
LOADMAX/2
(
)
DS(ON)
)
P
GATE
DT
D LS SW
P
)
P
(
D(HS)
is the time/cycle that the low-side MOSFET
D(LS)
≅
and I
)
= 2
(
I
IN
=
PEAK
is the on-resistance of the high-side
⎛
⎜
⎝
= P
is the input voltage. To minimize con-
1
=
= P
≅
✕
VALLEY
−
is the maximum average inductor
V
I
V
LOADMAX
×
V
OUT
D(HS)COND
D(LS)COND
VLG
OUT
V
t
IN
fall
2
FALL
×
✕
+
are the maximum peak and
⎞
⎟ ×
⎠
I
2
I
f
VALLEY
IC Power Dissipation
SW
LOADMAX
I
and t
2
×
4
LOADMAX
✕
t
×
+ P
+ P
DT
( Q
V
4
IN
RISE
×
×
D(LS)SW
D(HS)SW
GH
t
V
rise
DF
×
R
are the fall and
+ Q
)
DS ON
×
DF
×
V
R
f
IN
SW
(
GL
DS ON
DS(ON)
is the for-
SW
×
2
)
(
f
)
SW
is the
)
.