CY7C1380D-200AXC Cypress Semiconductor Corp, CY7C1380D-200AXC Datasheet - Page 6

• Manufacturer Part Number: CY7C1380D-200AXC
• Description: IC SRAM 18MBIT 200MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1380D-200AXC

• Memory Size: 18M (512K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3 ns
• Maximum Clock Frequency: 200 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 300 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2145; CY7C1380D-200AXC

Table 1. Pin Definitions
Document #: 38-05543 Rev. *F
A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQs, DQP
V
V
V
V
0
DD
SS
SSQ
DDQ
, A
1
2
3
A
C
Name
, BW
[2]
[2]
, BW
1
, A
B
D
X
Asynchronous
Asynchronous
Power Supply Power supply inputs to the core of the device.
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
I/O Ground
I/O Power
Ground
Supply
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
I/O-
I/O
Address inputs used to select one of the address locations. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE
are fed to the two-bit counter. .
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BW
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
only when a new external address is loaded.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
is loaded.
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act
as input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP
Ground for the core of the device.
Ground for the I/O circuitry.
Power supply for the I/O circuitry.
2
1
and CE
and CE
1
and CE
2
3
to select or deselect the device. CE
to select or deselect the device. ADSP is ignored if CE
3
to select or deselect the device. CE
X
are placed in a tri-state condition.
1
is deasserted HIGH.
Description
3
1
is sampled only when a new external address
, CE
2
2
, and CE
is sampled only when a new external
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
3
[2]
are sampled active. A1: A0
1
is HIGH. CE
X
and BWE).
1
is sampled
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