CY7C1370D-200BGXC Cypress Semiconductor Corp, CY7C1370D-200BGXC Datasheet

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... K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Functional Description The CY7C1370DV25 and CY7C1372DV25 are 2.5 V, 512 K × 36 and 1-Mbit × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states ...

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... CE1 CE2 CE3 ZZ Document Number: 38-05558 Rev. *H ADDRESS REGISTER A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS REGISTER 1 READ LOGIC Sleep Control CY7C1370DV25 CY7C1372DV25 DQs DQP T ...

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... TAP AC Switching Characteristics ............................... 14 2.5 V TAP AC Test Conditions ....................................... 15 2.5 V TAP AC Output Load Equivalent ......................... 15 TAP DC Electrical Characteristics and Operating Conditions ............................................. 15 Document Number: 38-05558 Rev. *H CY7C1370DV25 CY7C1372DV25 Scan Register Sizes ....................................................... 15 Identification Register Definitions ................................ 15 Identification Codes ....................................................... 16 119-ball BGA Boundary Scan Order ............................ 16 165-ball FBGA Boundary Scan Order .......................... 17 Maximum Ratings ...

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... DQa DQb DDQ 20 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ NC DQa 28 53 DQa DQPa CY7C1370DV25 CY7C1372DV25 167 MHz Unit 3.4 ns 275 DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa × 18 DQa 63 DQa DDQ ...

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... Pin Configurations (continued DDQ B NC/576M C NC/ DDQ DDQ DDQ NC/144M DDQ DDQ B NC/576M C NC/ DDQ DDQ DDQ NC/144M T NC/72M U V DDQ Document Number: 38-05558 Rev. *H 119-ball BGA Pinout CY7C1370DV25 (512 K × 36 ADV/ DQP CLK CEN DQP MODE NC/72M TMS TDI TCK ...

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... DDQ N DQP DDQ P NC/144M NC/72M A R MODE NC/36M NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M NC/72M A R MODE NC/36M A Document Number: 38-05558 Rev. *H 165-ball FBGA Pinout CY7C1370DV25 (512 K × 36 CEN CLK TDI A1 TDO ...

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... The direction of the pins is [17:0] –DQ are placed in a three-state condition. The outputs are controlled DQP is controlled controlled CY7C1370DV25 CY7C1372DV25 and DQP , BW controls DQ and DQP and DQP . d . During write s , DQP is controlled ...

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... Burst Read Accesses The CY7C1370DV25 and CY7C1372DV25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the ) is 2 ...

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... CY7C1372DV25) are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1370DV25/CY7C1372DV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs ...

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... Next NOP/write abort (begin burst) None Write abort (continue burst) Next Ignore clock edge (stall) Current Sleep mode None Partial Write Cycle Description Function (CY7C1370DV25) Read Write – No bytes written Write byte a – (DQ and DQP ) a a Write byte b – (DQ and DQP ...

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... DQP ) b b Write both bytes IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1370DV25/CY7C1372DV25 incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3 2.5 V I/O logic levels. The CY7C1370DV25/CY7C1372DV25 controller, instruction register, boundary scan register, bypass register, and ID register ...

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... The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP ) SS controller Shift-DR state. It also places all SRAM outputs into a high Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the CY7C1370DV25 CY7C1372DV25 Page [+] Feedback ...

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... TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE UNDEFINED CY7C1370DV25 CY7C1372DV25 TDOV t TDOX Page [+] Feedback ...

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... Notes 9. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register 10. Test conditions are specified using the load in TAP AC test Conditions. t Document Number: 38-05558 Rev. *H Description / ns CY7C1370DV25 CY7C1372DV25 Min Max Unit 50 – ns – 20 MHz 20 – ...

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... V OL DDQ V = 2.5 V DDQ V = 2.5 V DDQ GND < V < DDQ Bit Size (× 18 CY7C1372DV25 CY7C1370DV25 000 000 01011001000100101 01011001000010101 00000110100 00000110100 1 1 CY7C1370DV25 CY7C1372DV25 1.25V 50 50 20pF O Min Max Unit 2.0 – V 2.1 – V – 0.4 V – 0 –0.3 0.7 V – ...

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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 119-ball BGA Boundary Scan Order Bit # Ball ID Bit # Notes 12. Balls which are NC (No Connect) are pre-set LOW. 13. Bit pre-set HIGH. Document Number: 38-05558 Rev. *H Description [12, 13] Ball ID Bit # Ball CY7C1370DV25 CY7C1372DV25 Bit # Ball Internal Page [+] Feedback ...

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... G11 25 F11 26 E11 27 D11 28 G10 29 F10 30 E10 Notes 14. Balls which are NC (No Connect) are pre-set LOW. 15. Bit pre-set HIGH. Document Number: 38-05558 Rev. *H [14, 15] Bit # Ball ID 31 D10 32 C11 33 A11 34 B11 35 A10 36 B10 C10 CY7C1370DV25 CY7C1372DV25 Bit # Ball Internal Page [+] Feedback ...

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... All speed grades DD  V  /2), undershoot: V (AC) > –2 V (Pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1370DV25 CY7C1372DV25 + 0 Ambient DDQ Temperature 0 °C to +70 °C 2.5 V ± 5% –40 °C to +85 °C Min Max Unit 2.375 2.625 V 2.375 ...

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... Package Test conditions follow standard 28.66 test methods and procedures for measuring thermal 4.08 impedance, per EIA/JESD51 1667  2 DDQ GND 1538  INCLUDING JIG AND (b) SCOPE CY7C1370DV25 CY7C1372DV25 119 BGA 165 FBGA Unit Package Package 119 BGA 165 FBGA Unit ...

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... V minimum initially, before a read or write operation can be DD and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1370DV25 CY7C1372DV25 –200 –167 Unit Min Max Min Max 1 – ...

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... DOH CLZ D(A1) D(A2) D(A2+1) Q(A3) t BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1370DV25 CY7C1372DV25 OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) OEHZ t DOH t OELZ WRITE READ WRITE DESELECT ...

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... A3 A4 D(A1) Q(A2) Q(A3) READ WRITE STALL Q(A3) D(A4) DON’T CARE High-Z DON’T CARE is LOW. When CE is HIGH HIGH CY7C1370DV25 CY7C1372DV25 CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT UNDEFINED t ZZREC t RZZI DESELECT or READ Only is LOW HIGH ...

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... X = Pb-free; X Absent = Leaded Package Type 100-pin TQFP BZ = 165-ball FPBGA Speed Grade: XXX = 167 MHz / 200 MHz V25 = 2 Process Technology  90nm 137X 1370 = PL, 512 Kb × 36 (18 Mb) 1372 = PL × 18 (18 Mb) Marketing Code SRAMs Company ID Cypress CY7C1370DV25 CY7C1372DV25 Operating Range Commercial Commercial Page [+] Feedback ...

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... Package Diagrams Figure 1. 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm), 51-85050 Document Number: 38-05558 Rev. *H CY7C1370DV25 CY7C1372DV25 51-85050 *C Page [+] Feedback ...

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... Figure 2. 119-ball BGA (14 × 22 × 2.4 mm), 51-85115 Document Number: 38-05558 Rev. *H CY7C1370DV25 CY7C1372DV25 51-85115 *C Page [+] Feedback ...

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... Figure 3. 165-ball FPBGA (13 × 15 × 1.4 mm), 51-85180 Document Number: 38-05558 Rev. *H CY7C1370DV25 CY7C1372DV25 51-85180 *C Page [+] Feedback ...

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... TCK test clock TDI test data input TMS test mode select TDO test data output TQFP thin quad flat pack WE write enable Document Number: 38-05558 Rev. *H CY7C1370DV25 CY7C1372DV25 Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA ...

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... Document History Page Document Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05558 Orig. of REV. ECN No. Issue Date Change ** 254509 See ECN *A 288531 See ECN *B 326078 See ECN *C 418125 See ECN *D 475677 See ECN ...

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... Document Number: 38-05558 Rev. *H NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised October 20, 2010 CY7C1370DV25 CY7C1372DV25 PSoC Solutions psoc.cypress.com/solutions PSoC 1 ...