CAT24C02YI-GT3 ON Semiconductor, CAT24C02YI-GT3 Datasheet - Page 6
![IC EEPROM 2KBIT 400KHZ 8TSSOP](/photos/7/25/72557/cat24c02yi-gt3_sml.jpg)
CAT24C02YI-GT3
Manufacturer Part Number
CAT24C02YI-GT3
Description
IC EEPROM 2KBIT 400KHZ 8TSSOP
Manufacturer
ON Semiconductor
Specifications of CAT24C02YI-GT3
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
2K (256 x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP
Organization
256 K x 8
Interface Type
I2C
Maximum Clock Frequency
0.4 MHz
Access Time
900 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.7 V
Maximum Operating Current
2 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V , 2.5 V , 3.3 V , 5 V
Density
2Kb
Access Time (max)
900ns
Frequency (max)
400KHz
Write Protection
Yes
Data Retention
100Year
Operating Supply Voltage (typ)
1.8/2.5/3.3/5V
Package Type
TSSOP
Operating Temp Range
-40C to 85C
Supply Current
2mA
Operating Supply Voltage (min)
1.7V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
24C02YI-GT3
CAT24C02YI-GT3TR
CAT24C02YI-GT3TR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CAT24C02YI-GT3
Manufacturer:
MURATA
Quantity:
12 000
Company:
Part Number:
CAT24C02YI-GT3
Manufacturer:
ON Semiconductor
Quantity:
30 873
Part Number:
CAT24C02YI-GT3
Manufacturer:
ON/安森美
Quantity:
20 000
Company:
Part Number:
CAT24C02YI-GT3A
Manufacturer:
ON Semiconductor
Quantity:
1 500
Byte Write
condition and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge, the
Master sends the byte address that is to be written into the
address pointer of the CAT24Cxx. After receiving another
acknowledge from the Slave, the Master transmits the data
byte to be written into the addressed memory location. The
CAT24Cxx device will acknowledge the data byte and the
Master generates the STOP condition, at which time the
device begins its internal Write cycle to nonvolatile memory
(Figure 6). While this internal cycle is in progress (t
SDA output will be tri−stated and the CAT24Cxx will not
respond to any request from the Master device (Figure 7).
Page Write
write cycle, using the Page Write operation (Figure 8). The
Page Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating after
the data byte is transmitted, the Master is allowed to send up
to fifteen additional bytes. After each byte has been
transmitted the CAT24Cxx will respond with an
acknowledge and internally increments the four low order
address bits. The high order bits that define the page address
remain unchanged. If the Master transmits more than sixteen
bytes prior to sending the STOP condition, the address
counter ‘wraps around’ to the beginning of page and
previously transmitted data will be overwritten. Once all
In Byte Write mode, the Master sends the START
The CAT24Cxx writes up to 16 bytes of data in a single
BUS ACTIVITY:
* For the CAT24C01 a
MASTER
SLAVE
S
R
S
T
A
T
7
= 0
Figure 6. Byte Write Sequence
ADDRESS
SLAVE
WRITE OPERATIONS
WR
http://onsemi.com
), the
A
C
K
6
ADDRESS
sixteen bytes are received and the STOP condition has been
sent by the Master, the internal Write cycle begins. At this
point all received data is written to the CAT24Cxx in a single
write cycle.
Acknowledge Polling
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24Cxx initiates the internal write cycle.
The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24Cxx is still busy
with the write operation, NoACK will be returned. If the
CAT24Cxx has completed the internal write operation, an
ACK will be returned and the host can then proceed with the
next read or write operation.
Hardware Write Protection
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24Cxx. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24Cxx will not acknowledge the data byte
and the Write request will be rejected.
Delivery State
a
BYTE
7
The acknowledge (ACK) polling routine can be used to
With the WP pin held HIGH, the entire memory is
The CAT24Cxx is shipped erased, i.e., all bytes are FFh.
− a
0
C
A
K
d
BYTE
DATA
7
− d
0
A
C
K
P
O
S
T
P