M95640-WMN6T STMicroelectronics, M95640-WMN6T Datasheet - Page 27

IC EEPROM 64KBIT 10MHZ 8SOIC

M95640-WMN6T

Manufacturer Part Number
M95640-WMN6T
Description
IC EEPROM 64KBIT 10MHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheet

Specifications of M95640-WMN6T

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
10MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-1947-2

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M95640, M95640-W, M95640-R, M95640-DR
Figure 16. Read Lock Status sequence
6.10
Lock ID
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the
instruction code, the address and a data byte on Serial Data input (D), and driving Chip
Select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't
Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
he eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write
cycle which duration is t
instruction sequence is shown in
Figure 17. Lock ID sequence
W
(specified in
Doc ID 16877 Rev 15
Figure
Table
17.
18,
Table
19,
Table 20
and
Table
21). The
Instructions
27/48

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