CY7C144AV-25AC Cypress Semiconductor Corp, CY7C144AV-25AC Datasheet - Page 11
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CY7C144AV-25AC
Manufacturer Part Number
CY7C144AV-25AC
Description
IC SRAM 64KB DUAL 64-TQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C144AV-25AC.pdf
(20 pages)
Specifications of CY7C144AV-25AC
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
64K (8K x 8)
Speed
25ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C144AV-25AC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Document #: 38-06051 Rev. *C
Write Cycle No. 2: CE Controlled Timing
Write Cycle No. 1: R/W Controlled Timing
Notes:
29. R/W must be HIGH during all address transitions.
30. A write occurs during the overlap (t
31. t
32. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
33. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. To access RAM, CE = V
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
CE
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
to be placed on the bus for the required t
as short as the specified t
HA
[34]
[34]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
R/W
R/W
OE
IL
PWE
, SEM = V
.
t
t
(continued)
SA
SA
SCE
IH
Note 35
.
or t
SD
PWE
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
) of a LOW CE or SEM.
t
[29, 30, 31, 36]
HZWE
[29, 30, 31, 32]
[33]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[32]
t
t
SD
SD
PWE
or (t
HZWE
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
t
t
HA
HA
t
t
+ t
HD
HD
SD
t
LZWE
) to allow the I/O drivers to turn off and data
CY7C007AV/017AV
t
HZOE
[33]
Note 35
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