CY7C0251AV-25AC Cypress Semiconductor Corp, CY7C0251AV-25AC Datasheet
CY7C0251AV-25AC
Specifications of CY7C0251AV-25AC
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CY7C0251AV-25AC Summary of contents
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... BUSY is an output in master mode and an input in slave mode. Cypress Semiconductor Corporation Document #: 38-06052 Rev. *B • Automatic power-down • Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • ...
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Pin Configurations I/O 10L 5 I/O 6 11L I/O 12L 7 I/O 13L 8 GND 9 I/O 10 14L I/O 11 15L GND I I/O 15 ...
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... NC 4 I/O10L 5 I/O11L 6 I/O12L 7 I/O13L 8 GND 9 I/O14L 10 I/O15L 11 VCC 12 GND 13 I/O0R 14 I/O1R 15 I/O2R 16 VCC 17 I/O3R 18 I/O4R 19 I/O5R 20 I/O6R Notes the CY7C0251AV. 12L the CY7C0251AVC. 12R Document #: 38-06052 Rev. *B Top View 100-Pin TQFP CY7C0241AV (4K × 18) CY7C0251AV (8K × 18 CY7C026AV (16K × 16 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV ...
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Pin Configurations (continued I/O 8L I/O 17L I/O 11L I/O 12L I/O 13L I/O 14L GND I/O 15L I/O 16L V CC GND I/O 0R I I/O 3R I/O 4R I/O 5R I/O ...
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... Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM ...
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... HIGH during SEM LOW). A semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port ...
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... Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Notes: 9. See Functional Description for specific highest memory locations by device. 10. If BUSY =L, then no change. R 11. If BUSY =L, then no change ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature .................................– +150 C Ambient Temperature with Power Applied.............................................– +125 C Supply Voltage to Ground Potential ............... –0.5V ...
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AC Test Loads and Waveforms 3. 590 OUTPUT 435 (a) Normal Load (Load 1) Switching Characteristics Over the Operating Range Parameter Read Cycle t Read Cycle Time RC t Address to Data ...
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Switching Characteristics Over the Operating Range Parameter t Data Hold From Write End HD [21, 22] t R/W LOW to High Z HZWE [21, 22] t R/W HIGH to Low Z LZWE [23] t Write Pulse to Data Delay WDD ...
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Switching Waveforms Read Cycle No.1 (Either Port Address Access) ADDRESS t OHA DATA OUT PREVIOUS DATA VALID Read Cycle No.2 (Either Port CE/OE Access) CE and DATA OUT I CC CURRENT I SB [27, 29, 30, ...
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Switching Waveforms (continued) Write Cycle No.1: R/W Controlled Timing ADDRESS OE [36, 37 R/W NOTE 39 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [36, 37 R/W DATA IN Notes: ...
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Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS 0 2 SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A – ...
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Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 45 LOW. ...
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Switching Waveforms (continued) Busy Timing Diagram No.1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE ValidFirst: R ADDRESS L BUSY L Busy Timing Diagram No.2 (Address Arbitration) Left Address ...
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Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT R : ADDRESS WRITE 1FFF (OR 1/3FFF R/W L INT R t INS Right Side Clears INT R : ADDRESS R ...
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... Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C0241AV-20AC 25 CY7C0241AV-25AC 8K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C0251AV-20AC 25 CY7C0251AV-25AC 16K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C036AV-20AC 25 CY7C036AV-25AC CY7C036AV-25AI Document #: 38-06052 Rev. *B CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Package Name Package Type ...
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... Document #: 38-06052 Rev. *B © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...
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... Document History Page Document Title: CY7C024AV/CY7C025AV/CY7C026AV/CY7C0241AV/CY7C0251AV/CY7C036AV 3.3V 4K/8K/16K x 16/18 Dual Port Static RAM Document Number: 38-06052 REV. ECN NO. Issue Date ** 110204 11/11/01 *A 122302 12/27/02 *B 128958 9/03/03 Document #: 38-06052 Rev. *B Orig. of Change SZV Change from Spec number: 38-00838 to 38-06052 RBI Power up requirements added to Maximum Ratings Information ...