CAT24C128LI-G ON Semiconductor, CAT24C128LI-G Datasheet - Page 4

• Manufacturer Part Number: CAT24C128LI-G
• Description: IC EEPROM 128KBIT 400KHZ 8DIP
• Manufacturer: ON Semiconductor

Specifications of CAT24C128LI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 128K (16K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Organization: 16 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 24C128LI-G

Power−On Reset (POR)
circuitry which protects the device against powering up in
the wrong state.
V
Reset mode when V
This bi−directional POR feature protects the device against
‘brown−out’ failure following a temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A
When not driven, these pins are pulled LOW internally.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Functional Description
(I
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24C128 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected to
the bus as determined by the device address inputs A
and A
I
two wires are connected to the V
2
CC
0
2
C Bus Protocol
The CAT24C128 incorporates Power−On Reset (POR)
The CAT24C128 will power up into Standby mode after
The CAT24C128 supports the Inter−Integrated Circuit
The I
C) Bus data transmission protocol, which defines a device
, A
exceeds the POR trigger level and will power down into
1
2
.
and A
2
C bus consists of two ‘wires’, SCL and SDA. The
2
: The Address pins accept the device address.
CC
drops below the POR trigger level.
CC
supply via pull−up
http://onsemi.com
0
, A
1
,
4
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
busy (see A.C. Characteristics).
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
Device Addressing
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations (Figure 3).
The next 3 bits, A
devices and must match the state of the external address pins.
The last bit, R/W, specifies whether a Read (1) or Write (0)
operation is to be performed.
Acknowledge
with an acknowledge (ACK) by pulling down the SDA line
during the 9
acknowledge all address bytes and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
Data transfer may be initiated only when the bus is not
During data transfer, the SDA line must remain stable
The Master initiates data transfer by creating a START
After processing the Slave address, the Slave responds
th
clock cycle (Figure 4). The Slave will also
2
, A
1
and A
0
, select one of 8 possible Slave
th
clock cycle. As