VRS51C1100-40-Q Cypress Semiconductor, VRS51C1100-40-Q Datasheet - Page 14

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VRS51C1100-40-Q

Manufacturer Part Number
VRS51C1100-40-Q
Description
8-bit Microcontrollers - MCU 128K+1K 40MHz 5V
Manufacturer
Cypress Semiconductor
Datasheet

Specifications of VRS51C1100-40-Q

Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Program Memory Size
64 KB
Data Ram Size
1 KB
Operating Supply Voltage
4.5 V to 5.5 V
Package / Case
QFP-44
Mounting Style
SMD/SMT
Data Rom Size
128 B
Interface Type
UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
36
Number Of Timers
3
Program Memory Type
Flash
Factory Pack Quantity
96
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Input/Output Ports
The VRS51C1100 has 36 bi-directional lines grouped
into four 8-bit I/O ports and one 4-bit I/O port. These
I/Os can be individually configured as inputs or
outputs.
With the exception of the P0 I/Os, which are of the
open drain type, each I/O consists of a transistor
connected to ground and a weak, transistor-based pull-
up resistor.
Writing a 0 in a given I/O port bit register will activate
the transistor connected to Vss and bring the I/O to a
low level.
Writing a 1 into a given I/O port bit register deactivates
the transistor between the pin and ground. In this case,
an internal weak pull-up resistor will bring the pin to a
high level (except for Port 0, which is open-drain).
To use a given I/O as an input, a 1 must be written into
its associated port register bit. By default, upon reset
all the I/Os are configured as inputs. The VRS51C1100
I/O ports are not designed to source current.
Structure of the P1, P2, P3 and P4 Ports
The
structure of the P1, P2, P3 and P4 port I/Os. For these
ports, the output stage is composed of a transistor (X1)
and a transistor set configured as a weak pull-up. Note
that the figure below does not show the intermediary
logic that connects the register’s output and the output
stage because this logic varies with the auxiliary
function of each port.
F
Each line may be used independently as a logical
input or output. When used as an input, the
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Internal Bus
IGURE
VRS51C1100
Write to
Register
Read Register
7: G
following
Read Pin
ENERAL
S
TRUCTURE OF THE
figure
D Flip-Flop
O
demonstrates
UTPUT
Q
Q
S
TAGE OF
P1, P2, P3
Vcc
X1
Pull-up
Network
the
AND
P4
general
IC Pin
corresponding bit register must be high. This would
correspond to #Q=0 in Figure 7.
The transistor would be off (open-circuited) and current
would flow from the VCC to the pin, generating a
logical high at the output. Note that if an external
device with a logical low value is connected to the pin,
the current will flow out of the pin.
The presence of the pull-up resistance, even when the
I/O’s are configured as inputs, means that a small
current is likely to flow from the VRS51C1100 I/O’s
pull-up resistors to the driving circuit when the inputs
are driven low. For this reason, the VRS51C1100 I/O
ports P1, P2, P3 and P4 are called “quasi bi-
directional”.
Structure of Port 0
The internal structure of P0 is shown in the next figure.
The auxiliary function of this port requires a particular
logic. As opposed to the other ports, P0 is truly bi-
directional. In other words, when used as an input, it is
considered to be in a floating logical state (high
impedance state). This arises from the absence of the
internal pull-up resistance. The pull-up resistance is
actually replaced by a transistor that is only used when
the port is configured to access external memory/data
bus (EA=0).
When used as an I/O port, P0 acts as an open drain
port and the use of an external pull-up resistor is likely
to be required for most applications.
When P0 is used as an external memory bus input (for
a MOVX instruction, for example), the outputs of the
register are automatically forced to 1.
F
Internal Bus
IGURE
Write to
Register
Read Register
8: P
Read Pin
ORT
P0’
S PARTICULAR STRUCTURE
D Flip-Flop
Q
Q
Address A0/A7
Control
page 14 of 50
Vcc
X1
IC Pin

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