93C46B/ST Microchip Technology, 93C46B/ST Datasheet - Page 10
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93C46B/ST
Manufacturer Part Number
93C46B/ST
Description
IC EEPROM 1KBIT 2MHZ 8TSSOP
Manufacturer
Microchip Technology
Specifications of 93C46B/ST
Memory Size
1K (64 x 16)
Package / Case
8-TSSOP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
2MHz
Interface
Microwire, 3-Wire Serial
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Organization
64 K x 16
Interface Type
2-Wire
Maximum Clock Frequency
2 MHz
Access Time
6 ms
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Current
1.5 mA
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Operating Supply Voltage
2.5 V, 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
93C46B/ST
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.9
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA46A/B/C and 93LC46A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C46A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction
but the chip must be in the EWEN status.
FIGURE 2-10:
FIGURE 2-11:
DS21749D-page 10
CLK
CLK
DO
V
DO
CS
CS
DI
DI
CC
must be
WRITE ALL (WRAL)
4.5V for proper operation of WRAL.
1
1
HIGH-Z
HIGH-Z
WRAL TIMING FOR 93AA AND 93LC DEVICES
WRAL TIMING FOR 93C DEVICES
0
0
0
0
0
0
1
1
X
X
•••
•••
X
X
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
V
Dx
Dx
CC
Note:
must be
CSL
•••
•••
).
Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
D0
D0
4.5V for proper operation of WRAL.
T
T
CSL
CSL
T
WL
T
WL
BUSY
BUSY
2003 Microchip Technology Inc.
T
T
SV
SV
READY
READY
HIGH-Z
HIGH-Z
T
T
CZ
CZ