93C46B/ST Microchip Technology, 93C46B/ST Datasheet - Page 11
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93C46B/ST
Manufacturer Part Number
93C46B/ST
Description
IC EEPROM 1KBIT 2MHZ 8TSSOP
Manufacturer
Microchip Technology
Specifications of 93C46B/ST
Memory Size
1K (64 x 16)
Package / Case
8-TSSOP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
2MHz
Interface
Microwire, 3-Wire Serial
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Organization
64 K x 16
Interface Type
2-Wire
Maximum Clock Frequency
2 MHz
Access Time
6 ms
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Current
1.5 mA
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Operating Supply Voltage
2.5 V, 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
93C46B/ST
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.0
TABLE 3-1:
3.1
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
3.2
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
clock low time (T
freedom in preparing opcode, address and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
2003 Microchip Technology Inc.
ORG/NC
Name
CLK
V
Vss
DO
NC
CS
DI
PIN DESCRIPTIONS
CC
Chip Select (CS)
Serial Clock (CLK)
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
CKL
PIN DESCRIPTIONS
). This gives the controlling master
SOIC/PDIP/
TSSOP
MSOP/
1
2
3
4
5
6
7
8
SOT-23
N/A
N/A
CSL
5
4
3
1
2
6
) between
CKH
) and
Rotated SOIC
3
4
5
6
7
8
1
2
data bits before an instruction is executed. CLK and DI
then become don't care inputs waiting for a new Start
condition to be detected.
3.3
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
3.4
Data Out (DO) is used in the READ mode to output
data synchronously with the CLK input (T
positive edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum Chip Select
low time (T
has been initiated.
The Status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
3.5
When the ORG pin is connected to V
(x16) memory organization is selected. When the ORG
pin is tied to V
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX46A devices are always x8 organization and
93XX46B devices are always x16 organization.
Note:
Chip Select
Serial Clock
Data In
Data Out
Ground
Organization / 93XX46C
No internal connection / 93XX46A/B
No Internal Connection
Power Supply
Data In (DI)
Data Out (DO)
Organization (ORG)
Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
CSL
) and an ERASE or WRITE operation
SS
or Logic LO, the (x8) memory
Function
CC
DS21749D-page 11
or Logic HI, the
PD
after the