AT88SC1003-09ET-00 Atmel, AT88SC1003-09ET-00 Datasheet
AT88SC1003-09ET-00
Specifications of AT88SC1003-09ET-00
Related parts for AT88SC1003-09ET-00
AT88SC1003-09ET-00 Summary of contents
Page 1
... After personalization of the memory by the issuer, an internal fuse is blown that secures critical memory areas of the device and configures the IC for use by the end customer. The action of blowing this fuse is irreversible. The AT88SC1003 is manufactured using low-power CMOS technology. EEPROM programming func- tions are accomplished using an internally generated high-voltage pump for single voltage supply operation ...
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... Pin Configuration Pad Description VCC Supply Voltage GND Ground CLK Serial Clock Input I/O Serial Data Input/Output RST Reset Input PGM Program Input FUS Fuse Input Figure 2-1. Figure 2-2. AT88SC1003 2 ISO Module Contact Card Module Contact RST = C2 CLK = C3 FUS = C4 Block Diagram V ...
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... Level 1: Security During Personalization by the Card Issuer AT88SC1003 die and modules are delivered with the issuer fuse intact. Issuer personalization is completed at this level. Security code validation is required to allow access to personalize the EEPROM memory. During personalization, the manufacturer fuse may be blown to lock the manufacturer’ ...
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... See “Access Conditions After Personalization” Conditions: Issuer fuse = “0” (blown) FUS pin = “X” or Issuer fuse = “1” (not blown) FUS pin = “0” AT88SC1003 4 (Table 11-1 on page 13). (Table 12-1 on page 14). 2035C–SMEM–6/08 ...
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... Memory Map Table 5-1. AT88SC1003 Memory Diagram Bit Address Zone 0–15 FZ – Fabrication Zone 16–79 IZ – Issuer Zone 80–95 SC – Security Code 96–111 SCAC – Security Code Attempts Counter (only first 4 bits used) 112–175 CPZ – Code Protected Zone 176–431 AZ1 – ...
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... Read access is always allowed in the issuer zone. The security code is initially set by Atmel to protect the product during transportation to the card issuer. During personalization, this code must be entered and verified by the AT88SC1003 to allow access to the Security Code changed in either security mode ...
Page 7
... If the EC2EN fuse is blown (“0”), there is no limit to the number of erase operations in AZ2. After the issuer fuse is blown, the state of the EC2EN fuse is locked and cannot be changed. This EEPROM bit functions as a fuse that is used to change the security mode of the AT88SC1003 Issuer Fuse from Security Mode 1 (“ ...
Page 8
... Address location 1584 is designated as the erase bit for Application Zone 3. The erase protocol for an Application Zone 3 AT88SC1003 in Security Mode 2 requires that the erase key (EZ3) be verified, then an erase Erase Bit EB3 operation must be executed on the next bit following the erase key. This action will result in erasing the (1 bit) entire zone ...
Page 9
... Write A program operation that results in an EEPROM bit or word being set to a logic “0” state. An unwritten bit is defined as erased, or set to a logic “1” state. Write operations in the AT88SC1003 may be performed on individual bits after security code validation. In Security Level 2, write operations also require that the P1, P2 bit within an application zone is set to “ ...
Page 10
... This validation operation requires the user to find a bit in the SCAC, addresses 96–99, that is a logic “1”. A write is performed followed by an erase. The AT88SC1003 will validate that the comparison was correct by outputting a logic “1”, and SV will be set. After the erase, all 16 bits in the SCAC will also be erased ...
Page 11
... Table 8-1. Definition of AT88SC1003 Internal Flags (Continued) Flag Definition Application Zone 1 Erase E1 Flag Application Zone 2 Erase Flag with Erase Counter E2 Operation Enabled (EC2EN FUSE = “1”) Application Zone 2 Erase Flag with Erase Counter E2 Operation Disabled (EC2EN FUSE = “0”) Application Zone 3 Erase ...
Page 12
... EC2EN fuse is locked and cannot be changed. • Issuer Fuse This fuse is used to personalize the AT88SC1003 for end customer use additional EEPROM bit that can be programmed to a logic “0”. This is its “blown” state. Security of the device when the issuer fuse is a logic “1” is described in Security Level 2 when the issuer fuse is blown ...
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... AT88SC1003 (1) Read Erase Write yes no no yes no no yes no no yes yes yes yes yes yes yes no yes yes yes yes yes no no yes yes yes yes no no yes yes yes yes yes yes yes no no yes yes yes yes yes ...
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... Application Zone 1 (Bit 176) 4. 2nd bit of the Application Zone 1 (Bit 177) 5. 1st bit of the Application Zone 2 (Bit 480) 6. 2nd bit of the Application Zone 2 (Bit 481) 7. 1st bit of the Application Zone 3 (Bit 1024) 8. 2nd bit of the Application Zone 3 (Bit 1025) AT88SC1003 14 (5) (6) (7) (8) ...
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... E2 = “1” after a valid presentation of EZ2. 11 “1” after a valid presentation of EZ3. 13. Micro Operations The AT88SC1003 circuit micro operation modes are selected by the input logic levels on the control pins PGM, RST, and CLK and by the internal address. Timing for these operations is specified in Table 13-1 ...
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... FUNCTION: RESET The address is reset to “0”, and the first bit of the memory is driven by the AT88SC1003 on I/O after a reset. E1, E2, and E3 are reset when the address is reset to “0”. The reset operation has no effect on any of the other flags (SV, P1, P2, P3, R1, R2, R3). ...
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... AZ1, AZ2 and OPERATION: AZ3 Increment address counter to any bit within AZ1, AZ2, or AZ3. Security Mode 1 Perform “Erase Operation Sequence” as specified above. FUNCTION: This operation will erase the entire application zone. 2035C–SMEM–6/08 ) Table 12-1 and ). AT88SC1003 Table 11-1 and 17 ...
Page 18
... EC2EN fuse will logic “0” state. Set address counter between Address 992 and 1007. SV must be set. The FUS pin can be either a “0” “1”. Blowing Issuer Fuse RST pin = “0” Perform a write operation. Issuer fuse will logic “0” state. AT88SC1003 18 2035C–SMEM–6/08 ...
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... OL CLK = V open drain) CC AT88SC1003 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied ...
Page 20
... The circuit has an output with open drain. An external resistor is necessary between VCC and I/O in order to load the output. Table 15-3. Conditions of Dynamic Tests Pulse Levels of Input Reference Levels in Input Reference Levels in Output Rising and Falling Time of Signals AT88SC1003 20 Symbol Min Typ t 3.3 – ...
Page 21
... Figure 17-1. Reset Address CLK RST I/O Note: 2035C–SMEM–6/08 VCC CHIP R LOAD I/O 100 pF Test Ckt. Included 0 (internal address counter Output CLK should be low on the falling edge of RST. CLK may remain low while RST is pulsed. AT88SC1003 t DVR Data Valid 21 ...
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... Figure 17-2. Inc/Read Address CLK I/O Note: Figure 17-3. Erase/Write Address CLK PGM I/O Note: AT88SC1003 22 t CLK PGM and RST must both be low during a read cycle. I/O should not be driven (except by the external pullup resistor). Read Erase/Write A n SPR "1" (Erase) Valid or " ...
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... The address counter is incremented on the falling edge of CLK Hi-Z Output Input After the rising edge of CLK on the address immediately preceding the security code or erase keys, the I/O will be disabled (Hi-Z). This allows the input data to be set up before comparing the first bit of each code. AT88SC1003 n+1 ...
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... C = Write operation of a “0” over the exiting “1” The AT88SC1003 will output a “0” following the write operation. If the comparison is successful, the SV flag is set on the falling edge of CLK and the SCAC zone can be erased. ...
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... D = After the falling edge of CLK, the address is incremented and the state of the next bit is driven on the I/O contact. 2035C–SMEM–6/08 Compare EZ1 ( 431 432 433 478 CD CD 432 433 Input Input = Compare data (input). n AT88SC1003 Erase ( 480 479 1 CD 479 Output Input Read (C) (D) A 481 D 480 Output 25 ...
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... C = After the falling edge of CLK, the device will drive the I/O contact to the logic state of the existing data in Bit 768. The state of this bit is not affected by the AZ2 erase operation After the falling edge of CLK, the address is incremented and the state of the next bit is driven on the I/O contact. AT88SC1003 26 Compare EZ2 ...
Page 27
... EC2 that is found “1”. Bit 771 in this example is a “1”, so the write/erase sequence is begun with that bit Write operation of a “0” over the existing “1” The AT88SC1003 will output a “0” following the write operation. If the comparison is successful, the E2 flag is set and the AZ2 zone can be erased Erase operation F = The AT88SC1003 will output a “ ...
Page 28
... set to “1”, an erase operation on Bit 1584 will erase Bits 1024–1535 (AZ3). After the falling edge of CLK, the address is incremented. The E3 flag will be reset to “0” when the reset function is executed, or when the address is incremented beyond Address 1599. AT88SC1003 28 Compare EZ3 ...
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... Ordering Information Ordering Code AT88SC1003-09ET-00 AT88SC1003-09PT-00 AT88SC1003-10WI-00 (1) Package Type Description M2 – E Module M2 ISO 7816 Smart Card Module M2 – P Module M2 ISO 7816 Smart Card Module with Atmel Logo Note: 19. Packaging Information Ordering Code: 09ET-00 Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Round - Thickness: 0 ...
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